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Update TC_RR_1_1.py to match test spec changes. #24664
Update TC_RR_1_1.py to match test spec changes. #24664
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PR #24664: Size comparison from 3d104ef to 9574707 Increases (6 builds for cc13x2_26x2, cyw30739, esp32, psoc6, telink)
Decreases (9 builds for bl702, cc13x2_26x2, cyw30739, psoc6, telink)
Full report (54 builds for bl602, bl702, cc13x2_26x2, cyw30739, efr32, esp32, k32w, linux, mbed, nrfconnect, psoc6, qpg, telink)
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Step 1 was updated to remove any existing extra fabrics. Step 12 varied from the spec for the verified value.
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PR #24664: Size comparison from 86b064d to ae78a61 Increases (11 builds for bl602, bl702, cyw30739, esp32, nrfconnect, psoc6, telink)
Decreases (6 builds for cc13x2_26x2, k32w, nrfconnect, psoc6, telink)
Full report (54 builds for bl602, bl702, cc13x2_26x2, cyw30739, efr32, esp32, k32w, linux, mbed, nrfconnect, psoc6, qpg, telink)
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PR #24664: Size comparison from 15a135f to dc457e1 Increases (5 builds for bl702, esp32, telink)
Decreases (10 builds for bl602, cyw30739, psoc6, telink)
Full report (54 builds for bl602, bl702, cc13x2_26x2, cyw30739, efr32, esp32, k32w, linux, mbed, nrfconnect, psoc6, qpg, telink)
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Not sure how much it matters, but step 10 in the test plan specifies reading from ServerList instance of the descriptor cluster, so the test here doesn't match the test plan, even though it does the same thing.
I pulled the logs from the failing darwin test, and it seems to be a failure related to timing, not to your test. It's really hard to parse those logs to tell what failures are actuallly failures, but I THINK the errors are from
Anyway, I just kicked it again to see if it was a flake. |
* tag 'TE_23_02/rc2': (374 commits) Fix placeholder app shutdown to actually do a clean stack shutdown. (project-chip#24714) [chip-repl tests] Update tests that can pass (project-chip#24708) [repl tests] Allow the ability to run all tests in the test suite (including manual) (project-chip#24707) Rename silabs/types.xml to silabs/types-silabs.xml to prevent it to be loaded before chip/chip-types.xml since zcl-loader-silabs.js::parseZclFiles reorder the files if it match types.xml (project-chip#24710) Replace more arm64 nodeps-clang variants with just nodeps as they are mutually exclusive (project-chip#24704) Fix cloudbuild targets: It is "all-clusters" and not "all-clusters-app" (project-chip#24703) [Telink] Improve the Identify Implementation & Update every image to 0.6.35 (project-chip#24690) Add ability to list all YAML tests and manually run them from the test runner (project-chip#24629) silabs_fix_lighting_app_lcd (project-chip#24661) TC-ACE-1.4 automation (project-chip#24157) Update TC_RR_1_1.py to match test spec changes. (project-chip#24664) [nrfconnect] Fixed window covering compilation failure (project-chip#24700) [Telink] Logs optimization (project-chip#24693) [tv-app + YAML tests] Update the yaml tests to use the correct formatting for the responses since CurrentChannel is a struct (project-chip#24696) [YAML tests] Add PICS code to Color Control WaitForDelay steps (project-chip#24699) chip-repl tests: xml parsing to report location of where unrecognized handlers reside (project-chip#24674) Remove Basic SWBuildId extension from zll.xml since there is no cluster with this code (0x0000) (project-chip#24689) [Thermostat Cluster] Move related bitmaps/enums from silabs/types.xml to chip/thermostat-cluster.xml (project-chip#24694) [darwin] Add [WiFi/Ethernet]NetworkDiagnosticsFeature bitmaps and their values to darwin availability register (project-chip#24692) Less XML parsing, resulting in less errors (project-chip#24667) ...
* Update TC_RR_1_1.py to match test spec changes. Step 1 was updated to remove any existing extra fabrics. Step 12 varied from the spec for the verified value. * Read back fabric indexes during TC_RR_1_1.py
The following fixes were applied: