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Creating a custom Daughterboard
This page is a guideline on how to create a custom Daughterboard for Hive. First of all, please check if you could use any existing implementation. All the available daughterboards are listed in this readme file with their respective targets. The KiCad schematics of each daughterboard are located at the same location of this readme in the Hive repository.
Generally there are no specific guides on how to organize the targets on the Daughterboards, it is preferred to group the Daughterboards by target architecture, manufacturer or even product line if possible.
In order to ease the creation of a new Daughterboard the Hive repository contains a Daughterboard template KiCad Project. Simply clone the repo and copy the template. Make sure to rename the files to a name which matches your new Daughterboard.
There is one schematic for each target (target0.sch, target1.sch, ...). Please place your target and the corresponding parts into one of those schematics and connect them accordingly. For the proper wiring of the debug connections, please follow the recommendations of your target's documentation. The GPIO generally don't need any external pull resistors, unless required by the target. The UART TX and UART RX connections need to be connected to the respective bus connectors of the target (TX to RX, RX to TX).
If there are any unused debug connections it is recommended to tie those connections to ground via a pulldown resistor.
Once you've finished your Daughterboard and verified the design, feel free to submit a pull request so we can integrate it into the Daughterboard collection in the repository.
The below listed things are important to know in order to not run into any design issues.
The Daughterboard receives a supply of 5V as well as 3.3V via the connector on the Target Stack Shield. This means you can generally use targets which require a 5V power supply. All GPIO and probe connections to the target are 5V tolerant. The bus switches on the Target stack shield do an automatic level shifting of 5V to 3.3V. It is important to note that the received logic level to any 5V supplied target from the connected channel will still retain the 3.3V logic levels. Please make sure beforehand that the device can deal with 3.3V level logic signals. Otherwise level shifting is required! The minimum logic level is 3.3V if a target cannot meet this requirement level shifting is required as well.
Certain areas of the Daughterboard have strict part height limitations due to the hardware design of the Target Stack shield. Those areas are marked in the daughterboard template PCB layout file Cmts.User layer. Do not exceed those limitations to make sure the board fits into the Target Stack Shield.
The PCB thickness of the Daughterboard should be 0.8mm in order to fit the PCI connector.