Add Verilog ASIC implementation in README.md

[28add11]

Hello,
I've written a decoder in Verilog for the Tiny Tapeout program and submitted it for manufacturing into an ASIC! The chip won't be in anyone's hands for a while, so the hardware version is untested, but it works in simulation and I hope that is enough reason to be added. My one concern is that it doesn't handle any files or frames, it only decodes things on a sample by sample basis. I plan to write some code to handle this in the future, but for now I hope this qualifies as an "implementation" even with the limited functionality.
Thanks!

[amstan]

:O

This is what I get for sleeping on it.

I'm really looking forward to reading your implementation!

My one concern is that it doesn't handle any files or frames, it only decodes things on a sample by sample basis.

Don't worry, file metadata parsing is not hardware's job. Think of this used in combination with some kind of extra software drivers that do understand files.

My QOI fpga stuff did something similar. I took the original C code apart and rewrote the tight loops to use the fpga instead (linked it all back together using verilator).

[28add11]

Haha, the early bird gets the worm it would seem 😁! Please let me know if you find anything I could improve, I'm still super new to the hardware side of things, and any way to make it more compatible/better would be much appreciated not to mention my lack of actual hardware testing affecting things.

I'll have to check out your qoi implementation, it sounds pretty interesting. Thanks for sharing that!