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move pc increment to CPU.step
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pcasaretto committed Apr 7, 2024
1 parent 87e7f90 commit f407b17
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Showing 7 changed files with 29 additions and 84 deletions.
22 changes: 0 additions & 22 deletions src/instructions/adc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,6 @@ pub fn adc(target: RegisterTarget) -> impl Fn(&mut CPU) {
cpu.registers.f.subtract = false;
cpu.registers.f.zero = new_value == 0;
cpu.registers.f.half_carry = (current_value & 0xF) + (target_value & 0xF) > 0xF;

cpu.pc = cpu.pc.wrapping_add(1);
}
}

Expand Down Expand Up @@ -133,24 +131,4 @@ mod tests {
adc(RegisterTarget::C)(&mut cpu);
assert!(cpu.registers.f.half_carry);
}

#[test]
fn test_adc_advance_pc() {
let mut cpu = CPU {
pc: 123,
..Default::default()
};
adc(RegisterTarget::C)(&mut cpu);
assert_eq!(cpu.pc, 124);
}

#[test]
fn test_adc_advance_pc_wrap() {
let mut cpu = CPU {
pc: 0xFFFF,
..Default::default()
};
adc(RegisterTarget::C)(&mut cpu);
assert_eq!(cpu.pc, 0);
}
}
22 changes: 0 additions & 22 deletions src/instructions/add.rs
Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,6 @@ pub fn add(target: RegisterTarget) -> impl Fn(&mut CPU) {
cpu.registers.f.zero = new_value == 0;
cpu.registers.f.subtract = false;
cpu.registers.f.half_carry = (current_value & 0xF) + (target_value & 0xF) > 0xF;

cpu.pc = cpu.pc.wrapping_add(1);
}
}

Expand Down Expand Up @@ -112,24 +110,4 @@ mod tests {
add(RegisterTarget::C)(&mut cpu);
assert!(cpu.registers.f.half_carry);
}

#[test]
fn test_add_advance_pc() {
let mut cpu = CPU {
pc: 123,
..Default::default()
};
add(RegisterTarget::C)(&mut cpu);
assert_eq!(cpu.pc, 124);
}

#[test]
fn test_add_advance_pc_wrap() {
let mut cpu = CPU {
pc: 0xFFFF,
..Default::default()
};
add(RegisterTarget::C)(&mut cpu);
assert_eq!(cpu.pc, 0);
}
}
24 changes: 1 addition & 23 deletions src/instructions/inc.rs
Original file line number Diff line number Diff line change
@@ -1,32 +1,10 @@
use crate::CPU;

pub fn inc_sp() -> impl Fn(&mut CPU) {
move |cpu: &mut CPU| {
cpu.pc = cpu.pc.wrapping_add(1);
}
move |_: &mut CPU| {}
}

#[cfg(test)]
mod tests {
use super::*;

#[test]
fn test_inc_sp() {
let mut cpu = CPU {
pc: 0xF012,
..Default::default()
};
inc_sp()(&mut cpu);
assert_eq!(cpu.pc, 0xF013);
}

#[test]
fn test_inc_sp_wrap() {
let mut cpu = CPU {
pc: 0xFFFF,
..Default::default()
};
inc_sp()(&mut cpu);
assert_eq!(cpu.pc, 0x0000);
}
}
30 changes: 24 additions & 6 deletions src/instructions/ld.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,23 +5,32 @@ pub fn ld_d16_u16(reg: Register16bTarget) -> impl Fn(&mut CPU) {
let low = cpu.bus.memory[(cpu.pc + 1) as usize];
let high = cpu.bus.memory[(cpu.pc + 2) as usize];
cpu.registers.set_u16(reg, u16::from_le_bytes([low, high]));
cpu.pc += 3;
cpu.pc = cpu.pc.wrapping_add(2);
}
}

pub fn ld_d8_u8(reg: RegisterTarget) -> impl Fn(&mut CPU) {
move |cpu: &mut CPU| {
let value = cpu.bus.memory[(cpu.pc + 1) as usize];
cpu.registers.set_u8(reg, value);
cpu.pc += 2;
cpu.pc = cpu.pc.wrapping_add(1);
}
}

pub fn ld_r_r(src: RegisterTarget, dest: RegisterTarget) -> impl Fn(&mut CPU) {
move |cpu: &mut CPU| {
let value = cpu.registers.get_u8(src);
cpu.registers.set_u8(dest, value);
cpu.pc += 1;
}
}

pub fn ld_hl_inc() -> impl Fn(&mut CPU) {
move |cpu: &mut CPU| {
let hl = cpu.registers.get_u16(Register16bTarget::HL);
let value = cpu.bus.memory[hl as usize];
cpu.registers.set_u8(RegisterTarget::A, value);
cpu.registers
.set_u16(Register16bTarget::HL, hl.wrapping_add(1));
}
}

Expand All @@ -37,7 +46,7 @@ mod tests {
cpu.bus.memory[2] = 0x02;
ld_d16_u16(Register16bTarget::BC)(&mut cpu);
assert_eq!(cpu.registers.get_u16(Register16bTarget::BC), 0x0201);
assert_eq!(cpu.pc, 3);
assert_eq!(cpu.pc, 2);
}

#[test]
Expand All @@ -52,7 +61,6 @@ mod tests {
};
ld_r_r(RegisterTarget::B, RegisterTarget::A)(&mut cpu);
assert_eq!(cpu.registers.get_u8(RegisterTarget::A), 0x01);
assert_eq!(cpu.pc, 1);
}

#[test]
Expand All @@ -61,6 +69,16 @@ mod tests {
cpu.bus.memory[1] = 0x01;
ld_d8_u8(RegisterTarget::B)(&mut cpu);
assert_eq!(cpu.registers.get_u8(RegisterTarget::B), 0x01);
assert_eq!(cpu.pc, 2);
assert_eq!(cpu.pc, 1);
}

#[test]
fn test_ld_hl_inc() {
let mut cpu = CPU::default();
cpu.registers.set_u16(Register16bTarget::HL, 0x1000);
cpu.bus.memory[0x1000] = 0x01;
ld_hl_inc()(&mut cpu);
assert_eq!(cpu.registers.get_u8(RegisterTarget::A), 0x01);
assert_eq!(cpu.registers.get_u16(Register16bTarget::HL), 0x1001);
}
}
3 changes: 2 additions & 1 deletion src/instructions/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,8 @@ pub fn from_byte(byte: u8) -> Box<dyn Fn(&mut CPU)> {
0x01 => Box::new(ld::ld_d16_u16(Register16bTarget::BC)),
0x11 => Box::new(ld::ld_d16_u16(Register16bTarget::DE)),
0x21 => Box::new(ld::ld_d16_u16(Register16bTarget::HL)),
0x33 => Box::new(inc::inc_sp()),
0x2A => Box::new(ld::ld_hl_inc()),
// 0x33 => Box::new(inc::inc_sp()),
0x40 => Box::new(ld::ld_r_r(RegisterTarget::B, RegisterTarget::B)),
0x41 => Box::new(ld::ld_r_r(RegisterTarget::B, RegisterTarget::C)),
0x42 => Box::new(ld::ld_r_r(RegisterTarget::B, RegisterTarget::D)),
Expand Down
11 changes: 1 addition & 10 deletions src/instructions/nop.rs
Original file line number Diff line number Diff line change
@@ -1,19 +1,10 @@
use super::super::*;

pub fn nop() -> impl Fn(&mut CPU) {
move |cpu: &mut CPU| {
cpu.pc += 1;
}
move |_: &mut CPU| {}
}

#[cfg(test)]
mod tests {
use super::*;

#[test]
fn test_nop() {
let mut cpu = CPU::default();
nop()(&mut cpu);
assert_eq!(cpu.pc, 1);
}
}
1 change: 1 addition & 0 deletions src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ impl Default for CPU {
impl CPU {
pub fn step(&mut self) {
let instruction_byte = self.bus.read_byte(self.pc);
self.pc = self.pc.wrapping_add(1);
let instruction = instructions::from_byte(instruction_byte);
instruction(self)
}
Expand Down

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