implement dec_r

src/instructions/dec.rs

@@ -0,0 +1,90 @@
+use crate::{RegisterTarget, CPU};
+
+pub fn dec_r(target: RegisterTarget) -> impl Fn(&mut CPU) {
+    move |cpu: &mut CPU| {
+        let current_value = cpu.read_single_register(target);
+        let (new_value, did_overflow) = current_value.overflowing_sub(1);
+        cpu.registers.set_u8(target, new_value);
+
+        cpu.registers.f.zero = new_value == 0;
+        cpu.registers.f.subtract = true;
+        cpu.registers.f.half_carry = current_value & 0x10 == 0x10;
+        cpu.registers.f.carry = did_overflow;
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use crate::{FlagsRegister, Registers};
+
+    #[test]
+    fn test_dec_r() {
+        let mut cpu = CPU {
+            registers: Registers {
+                b: 2,
+                ..Default::default()
+            },
+            ..Default::default()
+        };
+        dec_r(RegisterTarget::B)(&mut cpu);
+        assert_eq!(cpu.registers.b, 1);
+    }
+
+    #[test]
+    fn test_dec_r_overflow() {
+        let mut cpu = CPU {
+            registers: Registers {
+                b: 0,
+                ..Default::default()
+            },
+            ..Default::default()
+        };
+        dec_r(RegisterTarget::B)(&mut cpu);
+        assert_eq!(cpu.registers.b, 0xFF);
+    }
+
+    #[test]
+    fn test_dec_r_subtract_flag() {
+        let mut cpu = CPU {
+            registers: Registers {
+                f: FlagsRegister {
+                    subtract: false,
+                    ..Default::default()
+                },
+                ..Default::default()
+            },
+            ..Default::default()
+        };
+        dec_r(RegisterTarget::B)(&mut cpu);
+        assert!(cpu.registers.f.subtract);
+    }
+
+    #[test]
+    fn test_dec_r_half_carry_flag() {
+        let mut cpu = CPU {
+            registers: Registers {
+                b: 0x10,
+                f: FlagsRegister::from(0),
+                ..Default::default()
+            },
+            ..Default::default()
+        };
+        dec_r(RegisterTarget::B)(&mut cpu);
+        assert!(cpu.registers.f.half_carry);
+    }
+
+    #[test]
+    fn test_dec_r_carry_flag() {
+        let mut cpu = CPU {
+            registers: Registers {
+                b: 0,
+                f: FlagsRegister::from(0),
+                ..Default::default()
+            },
+            ..Default::default()
+        };
+        dec_r(RegisterTarget::B)(&mut cpu);
+        assert!(cpu.registers.f.carry);
+    }
+}

src/instructions/mod.rs

@@ -1,5 +1,6 @@
 mod adc;
 mod add;
+mod dec;
 mod inc;
 mod int;
 mod jmp;
@@ -31,6 +32,14 @@ pub fn from_byte(byte: u8) -> Box<dyn Fn(&mut CPU)> {
         0x2C => Box::new(inc::inc_r(RegisterTarget::L)),
         0x3C => Box::new(inc::inc_r(RegisterTarget::A)),
 
+        0x05 => Box::new(inc::inc_r(RegisterTarget::B)),
+        0x15 => Box::new(inc::inc_r(RegisterTarget::D)),
+        0x25 => Box::new(inc::inc_r(RegisterTarget::H)),
+        0x0D => Box::new(dec::dec_r(RegisterTarget::C)),
+        0x1D => Box::new(dec::dec_r(RegisterTarget::E)),
+        0x2D => Box::new(dec::dec_r(RegisterTarget::L)),
+        0x3D => Box::new(dec::dec_r(RegisterTarget::A)),
+
         0x20 => Box::new(jmp::jr_nz()),
 
         0x31 => Box::new(ld::ld_d16_u16(Register16bTarget::SP)),