Daniel Llorente [[email protected]]
Oliver Bründler [[email protected]]
This library is published under PSI HDL Library License, which is LGPL plus some additional exceptions to clarify the LGPL terms in the context of firmware development.
See Changelog
This tool automatically creates a testbench skeleton from a DUT VHDL file. Additional settings (e.g. clock frequencies) can be annotated in the VHDL file directly as comments.
The testbench generated can have two forms:
- Single File TB
- All code in a single file
- No separate test-cases
- Multi File TB
- If multiple testcases are specified, a package file is generated for each test-case
- This allows better organization of large testbenches
For more details, refer to the documentation
Stable releases are tagged in the form major.minor.bugfix.
- Whenever a change is not fully backward compatible, the major version number is incremented
- Whenever new features are added, the minor version number is incremented
- If only bugs are fixed (i.e. no functional changes are applied), the bugfix version is incremented
The required folder structure looks as given below (folder names must be matched exactly).
Alternatively the repository psi_fpga_all can be used. This repo contains all FPGA related repositories as submodules in the correct folder structure.
- Python
- PsiPyUtils (3.0.0 or higher)
- TbGenerator
- PIP
- PyQt5
- pyparsing