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add: testing framework and initial tests #14
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78277b1
add: testing utils
8ee7146
add: compare and swap pair test
f720368
add: instruction bitmask testing utility v1
73825a1
add: instruction bitmask testing utility v2
aad98d5
update: testing utils
2b15287
update: load register literal test v2
fc23a3c
add: compare and swap pair test
6ae8408
add: load store register pair tests
24c67b0
fix: remove redundant headers
9d20f9f
fix: make test names more readable
945503f
add: prefetch memory instruction test
0899c46
add: new tests
4a0c06a
fix: replace EXPECT_EQ with ASSERT_EQ for all tests so failing tests …
e01cd0e
fix: add missing argument for Cmake External Fetch
branylagaffe 36163ba
fix: ootb test compilation
3051947
fix: refactor testing utils
1859d38
fix: change file extensions to .cpp and .h, move "extern C" to trace.h
320d4b6
add: branch decoder tests
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,73 @@ | ||
| cmake_minimum_required(VERSION 3.14) | ||
| project(libqflex) | ||
|
|
||
| # GoogleTest requires at least C++14 | ||
| set(CMAKE_CXX_STANDARD 14) | ||
| set(CMAKE_CXX_STANDARD_REQUIRED ON) | ||
|
|
||
| include(FetchContent) | ||
| FetchContent_Declare( | ||
| googletest | ||
| URL https://github.com/google/googletest/archive/03597a01ee50ed33e9dfd640b249b4be3799d395.zip | ||
| ) | ||
| # For Windows: Prevent overriding the parent project's compiler/linker settings | ||
| set(gtest_force_shared_crt ON CACHE BOOL "" FORCE) | ||
| FetchContent_MakeAvailable(googletest) | ||
|
|
||
| enable_testing() | ||
|
|
||
| # Find GLib package | ||
| find_package(PkgConfig REQUIRED) | ||
| pkg_check_modules(GLIB REQUIRED glib-2.0) | ||
|
|
||
| # Include GLib directories | ||
| include_directories(${GLIB_INCLUDE_DIRS}) | ||
|
|
||
| add_executable( | ||
| compare-and-swap-pair ../libqflex/plugins/trace/memory-decoder.c testing-utils.cc compare-and-swap-pair.cc | ||
| ) | ||
| add_executable( | ||
| load-register-literal ../libqflex/plugins/trace/memory-decoder.c testing-utils.cc load-register-literal.cc | ||
| ) | ||
| add_executable( | ||
| load-store-register-pair-post-indexed ../libqflex/plugins/trace/memory-decoder.c testing-utils.cc load-store-register-pair-post-indexed.cc | ||
| ) | ||
| add_executable( | ||
| load-store-register-unscaled-immediate ../libqflex/plugins/trace/memory-decoder.c testing-utils.cc load-store-register-unscaled-immediate.cc | ||
| ) | ||
| add_executable( | ||
| load-store-register-immediate-post-indexed ../libqflex/plugins/trace/memory-decoder.c testing-utils.cc load-store-register-immediate-post-indexed.cc | ||
| ) | ||
|
|
||
| target_link_libraries( | ||
| compare-and-swap-pair | ||
| GTest::gtest_main | ||
| ${GLIB_LIBRARIES} | ||
| ) | ||
| target_link_libraries( | ||
| load-register-literal | ||
| GTest::gtest_main | ||
| ${GLIB_LIBRARIES} | ||
| ) | ||
| target_link_libraries( | ||
| load-store-register-pair-post-indexed | ||
| GTest::gtest_main | ||
| ${GLIB_LIBRARIES} | ||
| ) | ||
| target_link_libraries( | ||
| load-store-register-unscaled-immediate | ||
| GTest::gtest_main | ||
| ${GLIB_LIBRARIES} | ||
| ) | ||
| target_link_libraries( | ||
| load-store-register-immediate-post-indexed | ||
| GTest::gtest_main | ||
| ${GLIB_LIBRARIES} | ||
| ) | ||
|
|
||
| include(GoogleTest) | ||
| gtest_discover_tests(compare-and-swap-pair) | ||
| gtest_discover_tests(load-register-literal) | ||
| gtest_discover_tests(load-store-register-pair-post-indexed) | ||
| gtest_discover_tests(load-store-register-unscaled-immediate) | ||
| gtest_discover_tests(load-store-register-immediate-post-indexed) |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,170 @@ | ||
| #include <gtest/gtest.h> | ||
| #include "testing-utils.hh" | ||
|
|
||
| extern "C" { | ||
| #include "../libqflex/plugins/trace/trace.h" | ||
| } | ||
|
|
||
| struct mem_access mem_access; | ||
|
|
||
| Field sz("x"); | ||
| Field L("x"); | ||
| Field Rs("xxxxx"); | ||
| Field o0("x"); | ||
| Field Rt2("11111"); | ||
| Field Rn("xxxxx"); | ||
| Field Rt("xxxxx"); | ||
|
|
||
| Instruction bitmask("0", sz, "0010000", L, "1", Rs, o0, Rt2, Rn, Rt); | ||
|
|
||
| TEST(CompareAndSwapPair, CASP_32Bit) | ||
| { | ||
| sz = "0"; | ||
| L = "0"; | ||
| o0 = "0"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, true); // conditional store? | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_signed, false); | ||
| ASSERT_EQ(mem_access.is_pair, true); | ||
| ASSERT_EQ(mem_access.is_atomic, true); | ||
| ASSERT_EQ(mem_access.size, 0b10); | ||
| ASSERT_EQ(mem_access.accesses, 4); // conditional store? | ||
| } | ||
| } | ||
|
|
||
| TEST(CompareAndSwapPair, CASPL_32Bit) | ||
| { | ||
| sz = "0"; | ||
| L = "0"; | ||
| o0 = "1"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, true); // conditional store? | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_signed, false); | ||
| ASSERT_EQ(mem_access.is_pair, true); | ||
| ASSERT_EQ(mem_access.is_atomic, true); | ||
| ASSERT_EQ(mem_access.size, 0b10); | ||
| ASSERT_EQ(mem_access.accesses, 4); // conditional store? | ||
| } | ||
| } | ||
|
|
||
| TEST(CompareAndSwapPair, CASPA_32Bit) | ||
| { | ||
| sz = "0"; | ||
| L = "1"; | ||
| o0 = "0"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, true); // conditional store? | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_signed, false); | ||
| ASSERT_EQ(mem_access.is_pair, true); | ||
| ASSERT_EQ(mem_access.is_atomic, true); | ||
| ASSERT_EQ(mem_access.size, 0b10); | ||
| ASSERT_EQ(mem_access.accesses, 4); // conditional store? | ||
| } | ||
| } | ||
|
|
||
| TEST(CompareAndSwapPair, CASPAL_32Bit) | ||
| { | ||
| sz = "0"; | ||
| L = "1"; | ||
| o0 = "1"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, true); // conditional store? | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_signed, false); | ||
| ASSERT_EQ(mem_access.is_pair, true); | ||
| ASSERT_EQ(mem_access.is_atomic, true); | ||
| ASSERT_EQ(mem_access.size, 0b10); | ||
| ASSERT_EQ(mem_access.accesses, 4); // conditional store? | ||
| } | ||
| } | ||
|
|
||
| TEST(CompareAndSwapPair, CASP_64Bit) | ||
| { | ||
| sz = "1"; | ||
| L = "0"; | ||
| o0 = "0"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, true); // conditional store? | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_signed, false); | ||
| ASSERT_EQ(mem_access.is_pair, true); | ||
| ASSERT_EQ(mem_access.is_atomic, true); | ||
| ASSERT_EQ(mem_access.size, 0b11); | ||
| ASSERT_EQ(mem_access.accesses, 4); // conditional store? | ||
| } | ||
| } | ||
|
|
||
| TEST(CompareAndSwapPair, CASPL_64Bit) | ||
| { | ||
| sz = "1"; | ||
| L = "0"; | ||
| o0 = "1"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, true); // conditional store? | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_signed, false); | ||
| ASSERT_EQ(mem_access.is_pair, true); | ||
| ASSERT_EQ(mem_access.is_atomic, true); | ||
| ASSERT_EQ(mem_access.size, 0b11); | ||
| ASSERT_EQ(mem_access.accesses, 4); // conditional store? | ||
| } | ||
| } | ||
|
|
||
| TEST(CompareAndSwapPair, CASPA_64Bit) | ||
| { | ||
| sz = "1"; | ||
| L = "1"; | ||
| o0 = "0"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, true); // conditional store? | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_signed, false); | ||
| ASSERT_EQ(mem_access.is_pair, true); | ||
| ASSERT_EQ(mem_access.is_atomic, true); | ||
| ASSERT_EQ(mem_access.size, 0b11); | ||
| ASSERT_EQ(mem_access.accesses, 4); // conditional store? | ||
| } | ||
| } | ||
|
|
||
| TEST(CompareAndSwapPair, CASPAL_64Bit) | ||
| { | ||
| sz = "1"; | ||
| L = "1"; | ||
| o0 = "1"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, true); // conditional store? | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_signed, false); | ||
| ASSERT_EQ(mem_access.is_pair, true); | ||
| ASSERT_EQ(mem_access.is_atomic, true); | ||
| ASSERT_EQ(mem_access.size, 0b11); | ||
| ASSERT_EQ(mem_access.accesses, 4); // conditional store? | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,134 @@ | ||
| #include <gtest/gtest.h> | ||
| #include "testing-utils.hh" | ||
|
|
||
| extern "C" { | ||
| #include "../libqflex/plugins/trace/trace.h" | ||
| } | ||
|
|
||
| struct mem_access mem_access; | ||
|
|
||
| Field opc("xx"); | ||
| Field VR("x"); | ||
| Field imm19("xxxxxxxxxxxxxxxxxxx"); | ||
| Field Rt("xxxxx"); | ||
|
|
||
| Instruction bitmask(opc, "011", VR, "00", imm19, Rt); | ||
|
|
||
| TEST(LoadRegister_Literal, LDR_32Bit) | ||
| { | ||
| opc = "00"; | ||
| VR = "0"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, false); | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_pair, false); | ||
| ASSERT_EQ(mem_access.is_atomic, false); | ||
| ASSERT_EQ(mem_access.size, 0b10); | ||
| ASSERT_EQ(mem_access.accesses, 1); | ||
| } | ||
| } | ||
|
|
||
| TEST(LoadRegister_Literal, LDR_SIMDFP_32Bit) | ||
| { | ||
| opc = "00"; | ||
| VR = "1"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, false); | ||
| ASSERT_EQ(mem_access.is_vector, true); | ||
| ASSERT_EQ(mem_access.is_pair, false); | ||
| ASSERT_EQ(mem_access.is_atomic, false); | ||
| ASSERT_EQ(mem_access.size, 0b10); | ||
| ASSERT_EQ(mem_access.accesses, 1); | ||
| } | ||
| } | ||
|
|
||
| TEST(LoadRegister_Literal, LDR_64Bit) | ||
| { | ||
| opc = "01"; | ||
| VR = "0"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, false); | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_pair, false); | ||
| ASSERT_EQ(mem_access.is_atomic, false); | ||
| ASSERT_EQ(mem_access.size, 0b11); | ||
| ASSERT_EQ(mem_access.accesses, 1); | ||
| } | ||
| } | ||
|
|
||
| TEST(LoadRegister_Literal, LDR_SIMDFP_64Bit) | ||
| { | ||
| opc = "01"; | ||
| VR = "1"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, false); | ||
| ASSERT_EQ(mem_access.is_vector, true); | ||
| ASSERT_EQ(mem_access.is_pair, false); | ||
| ASSERT_EQ(mem_access.is_atomic, false); | ||
| ASSERT_EQ(mem_access.size, 0b11); | ||
| ASSERT_EQ(mem_access.accesses, 1); | ||
| } | ||
| } | ||
|
|
||
| TEST(LoadRegister_Literal, LDRSW) | ||
| { | ||
| opc = "10"; | ||
| VR = "0"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, false); | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_pair, false); | ||
| ASSERT_EQ(mem_access.is_atomic, false); | ||
| ASSERT_EQ(mem_access.size, 0b10); | ||
| ASSERT_EQ(mem_access.accesses, 1); | ||
| } | ||
| } | ||
|
|
||
| TEST(LoadRegister_Literal, LDR_SIMDFP_128Bit) | ||
| { | ||
| opc = "10"; | ||
| VR = "1"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, true); | ||
| ASSERT_EQ(mem_access.is_store, false); | ||
| ASSERT_EQ(mem_access.is_vector, true); | ||
| ASSERT_EQ(mem_access.is_pair, false); | ||
| ASSERT_EQ(mem_access.is_atomic, false); | ||
| ASSERT_EQ(mem_access.size, 0b100); | ||
| ASSERT_EQ(mem_access.accesses, 1); | ||
| } | ||
| } | ||
|
|
||
| TEST(LoadRegister_Literal, PRFM) | ||
| { | ||
| opc = "11"; | ||
| VR = "0"; | ||
|
|
||
| for (uint32_t instr : bitmask) { | ||
| ASSERT_EQ(decode_armv8_mem_opcode(&mem_access, instr), true); | ||
| ASSERT_EQ(mem_access.is_load, false); | ||
| ASSERT_EQ(mem_access.is_store, false); | ||
| ASSERT_EQ(mem_access.is_vector, false); | ||
| ASSERT_EQ(mem_access.is_pair, false); | ||
| ASSERT_EQ(mem_access.is_atomic, false); | ||
| ASSERT_EQ(mem_access.size, 0b10); /* prefetch? */ | ||
| ASSERT_EQ(mem_access.accesses, 1); /* prefetch? */ | ||
| } | ||
| } |
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As somewhat expected, the tests do not build OOTB, because the decoder require some qemu includes (osdep).
Two options from here:
1. Add a FLAG from the CmakeList.txt file which switch the header in the aforementioned files
2. Use QEMU build system to build the test, tricky but good.
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Could you elaborate on the second option? How would it work?
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Implemented the first option for now.