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feat: Implement the new way to train the branch predictor. #93

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@xusine xusine commented Dec 10, 2024

Now the rediction and the training is decoupled:

  • Redirection can happen speculatively. Redirection requires to restore the branch history (for TAGE) and append the new history of the instruction triggering redirection (e.g., branches, resync request).
  • Training the branch predictor happens for all instructions in their commit stage. This step includes updating the BTB as well as update the corresponding counters in the TAGE.

This commit also cleans unused effects related to the branches.

xusine and others added 17 commits November 27, 2024 14:26
**Description**
If the instruction is predicted as branch but it is not a branch, it
does not trigger a branch misprediction.

**Steps to Reproduce**
Run data caching image with 2 coresAfter some time an instruction is
predicted as a taken branch modifying the PCExpected BehaviorAfter we
dispatch we should rollback the next instructions and give branch
feedback to the frontend

**Actual Behavior**
No rollback happens when we notice the instruction is not a branch
Register 31 is the stack pointer, and therefor cannot be used as a
results register.
DAIF register is not part of the PSTATE anymore (from QEMU perspective)
Small fix for DAIFset
*Description*
There are a couple problematic cases for memory decoding. Namely
prefetch instruction with register offset and atomic load stores (ldxr)

*Expected Behavior*
Prefetch instruction should be decoded as nop and ldxr register should
be decoded with blackbox as it is not implemented.

*Actual Behavior*
They are decoded as normal load store instructions.
*Description*
LDP and STP instructions load or store to 2 memory locations. It is
normally implemented as two uOps in hardware, but it is a single uOp in
flexus. This causes some unintended bugs where store-load forwarding
breaks etc.

*Steps to Reproduce*
Run data caching image with 2 coresAfter some time, there will be a
sequence of instructions as follows:str to address x + 8ldp to address x

*Expected Behavior*
Load pair should get a part of its value from str because the second
load value of the pair address matches the str address.

*Actual Behavior*
It does not forward because the addresses x and x+8 are not the same.
Now the rediction and the training is decoupled:
- Redirection can happen speculatively. Redirection requires to restore the branch history (for TAGE) and append the new history of the instruction triggering redirection (e.g., branches, resync request).
- Training the branch predictor happens for all instructions in their commit stage. This step includes updating the BTB as well as update the corresponding counters in the TAGE.

This commit also cleans unused effects related to the branches.
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2 participants