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    295 repositories

    • chimera-sdk

      Public
      Python
      •
      Apache License 2.0
      •2•2•6•3•Updated Dec 13, 2024Dec 13, 2024

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •18•76•1•2•Updated Dec 13, 2024Dec 13, 2024

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •46•276•3•5•Updated Dec 13, 2024Dec 13, 2024

    • pulp-nnx

      Public
      C
      •
      Apache License 2.0
      •0•4•1•0•Updated Dec 13, 2024Dec 13, 2024

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •50•205•9•18•Updated Dec 13, 2024Dec 13, 2024

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •29•102•7•5•Updated Dec 13, 2024Dec 13, 2024

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •21•58•4•5•Updated Dec 13, 2024Dec 13, 2024

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •6•40•0•0•Updated Dec 13, 2024Dec 13, 2024

    • chimera

      Public
      Python
      •
      Other
      •2•10•9•1•Updated Dec 12, 2024Dec 12, 2024

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •9•17•4•3•Updated Dec 12, 2024Dec 12, 2024

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •16•28•4•3•Updated Dec 12, 2024Dec 12, 2024

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •22•148•10•5•Updated Dec 12, 2024Dec 12, 2024

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •702•16•1•8•Updated Dec 12, 2024Dec 12, 2024

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •271•1.1k•44•10•Updated Dec 10, 2024Dec 10, 2024

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •13•17•7•1•Updated Dec 10, 2024Dec 10, 2024

    • regression_tests

      Public
      C
      •16•6•3•1•Updated Dec 10, 2024Dec 10, 2024

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •58•53•14•7•Updated Dec 10, 2024Dec 10, 2024

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•9•0•2•Updated Dec 10, 2024Dec 10, 2024

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •34•37•6•4•Updated Dec 10, 2024Dec 10, 2024

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •132•385•64•10•Updated Dec 9, 2024Dec 9, 2024

    • apb

      Public
      APB Logic
      SystemVerilog
      •
      Other
      •10•12•1•0•Updated Dec 6, 2024Dec 6, 2024

    • parspl

      Public
      0•0•0•0•Updated Dec 5, 2024Dec 5, 2024

    • ITA

      Public
      SystemVerilog
      •
      Other
      •4•18•0•1•Updated Dec 5, 2024Dec 5, 2024

    • cluster_icache

      Public
      An instruction cache for processor clusters, originally developed for the snitch cluster.
      SystemVerilog
      •
      Other
      •2•2•0•5•Updated Dec 4, 2024Dec 4, 2024

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •2•10•1•4•Updated Dec 4, 2024Dec 4, 2024

    • common_verification

      Public
      SystemVerilog modules and classes commonly used for verification
      SystemVerilog
      •
      Other
      •13•44•0•2•Updated Dec 4, 2024Dec 4, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •145•531•31•7•Updated Dec 4, 2024Dec 4, 2024

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •2•19•1•3•Updated Dec 3, 2024Dec 3, 2024

    • hwpe-ctrl

      Public
      IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •17•6•3•4•Updated Dec 2, 2024Dec 2, 2024

    • ManyRVData

      Public
      0•0•0•0•Updated Nov 28, 2024Nov 28, 2024