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    • Verilog
      Other
      2941023Updated Dec 3, 2024Dec 3, 2024
    • OpenROAD

      Public
      OpenROAD's unified application implementing an RTL-to-GDS Flow
      Verilog
      BSD 3-Clause "New" or "Revised" License
      571000Updated Oct 29, 2024Oct 29, 2024
    • C++
      GNU General Public License v3.0
      23000Updated Sep 11, 2024Sep 11, 2024
    • Run clang-tidy on Bazel C++ targets directly, efficiently, with caching enabled
      Starlark
      MIT License
      58000Updated Aug 22, 2024Aug 22, 2024
    • OpenSTA

      Public
      OpenSTA engine
      C++
      GNU General Public License v3.0
      174000Updated Aug 13, 2024Aug 13, 2024
    • A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
      C++
      MIT License
      36000Updated Jul 5, 2024Jul 5, 2024
    • TypeScript
      BSD 3-Clause "New" or "Revised" License
      0000Updated Jun 17, 2024Jun 17, 2024
    • clang-toolchain without gnu.
      Dockerfile
      12000Updated May 22, 2024May 22, 2024
    • Scala
      Other
      87000Updated Apr 3, 2024Apr 3, 2024
    • Stack trace visualizer
      Perl
      2k000Updated Mar 22, 2024Mar 22, 2024
    • Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
      C++
      MIT License
      62000Updated Mar 20, 2024Mar 20, 2024
    • Rocket Chip Generator
      Scala
      Other
      1.1k000Updated Mar 19, 2024Mar 19, 2024
    • chipyard

      Public
      An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
      C
      BSD 3-Clause "New" or "Revised" License
      657000Updated Feb 1, 2024Feb 1, 2024
    • Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
      Starlark
      Apache License 2.0
      45000Updated Dec 13, 2023Dec 13, 2023
    • MIT License
      0000Updated Dec 1, 2023Dec 1, 2023
    • Sphinx Extension which generates various types of diagrams from Verilog code.
      Python
      Apache License 2.0
      16000Updated Sep 26, 2023Sep 26, 2023
    • SonicBOOM: The Berkeley Out-of-Order Machine
      Scala
      BSD 3-Clause "New" or "Revised" License
      427000Updated Sep 16, 2023Sep 16, 2023
    • A sphinx extension that allows including wavedrom diagrams by using its text-based representation
      JavaScript
      MIT License
      19000Updated Sep 13, 2023Sep 13, 2023
    • volare

      Public
      Version manager (and builder) for the Google sky130 and gf180mcu Open PDK
      Python
      Apache License 2.0
      7000Updated Jan 4, 2023Jan 4, 2023
    • OpenLane

      Public
      OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
      Verilog
      Apache License 2.0
      379000Updated Jan 3, 2023Jan 3, 2023
    • Box of handy tools for Sphinx 🧰 📔
      Python
      MIT License
      8000Updated Mar 19, 2022Mar 19, 2022
    • Sphinx extension to include VCD (value change dump) files using GTKWave
      Python
      BSD 2-Clause "Simplified" License
      3000Updated Feb 16, 2022Feb 16, 2022
    • ⌚ Get the "last updated" time for each Sphinx page from Git
      Python
      BSD 2-Clause "Simplified" License
      9000Updated Jan 29, 2022Jan 29, 2022
    • Sphinx plugin for generating RST on the fly from data files and templates.
      Python
      Other
      19000Updated Sep 2, 2021Sep 2, 2021
    • Python
      Apache License 2.0
      51000Updated Feb 1, 2021Feb 1, 2021
    • Sphinx extension to embedd a pdf file viewer in documentation webpages
      Python
      MIT License
      5000Updated Mar 16, 2019Mar 16, 2019