CVS-43973: added HWC layout

inference-engine/include/ie_common.h

@@ -83,6 +83,7 @@ enum Layout : uint8_t {
 
     // Single image layouts
     CHW = 128,  //!< A single image layout (e.g. for mean image)
+    HWC = 129,  //!< A single image layout (e.g. for mean image)
 
     // 2D
     HW = 192,  //!< HW 2D layout
@@ -113,6 +114,7 @@ inline std::ostream& operator<<(std::ostream& out, const Layout& p) {
         PRINT_LAYOUT(OIHW);
         PRINT_LAYOUT(C);
         PRINT_LAYOUT(CHW);
+        PRINT_LAYOUT(HWC);
         PRINT_LAYOUT(HW);
         PRINT_LAYOUT(NC);
         PRINT_LAYOUT(CN);

inference-engine/include/ie_compound_blob.h

@@ -289,8 +289,8 @@ class INFERENCE_ENGINE_API_CLASS(BatchedBlob) : public CompoundBlob {
      * @brief Constructs a batched blob from a vector of blobs
      * @details All passed blobs should meet following requirements:
      * - all blobs have equal tensor descriptors,
-     * - blobs layouts should be one of: NCHW, NHWC, NCDHW, NDHWC, NC, CN, C, CHW
-     * - batch dimensions should be equal to 1 or not defined (C, CHW).
+     * - blobs layouts should be one of: NCHW, NHWC, NCDHW, NDHWC, NC, CN, C, CHW, HWC
+     * - batch dimensions should be equal to 1 or not defined (C, CHW, HWC).
      * Resulting blob's tensor descriptor is constructed using tensor descriptors
      * of passed blobs by setting batch dimension to blobs.size()
      *
@@ -302,8 +302,8 @@ class INFERENCE_ENGINE_API_CLASS(BatchedBlob) : public CompoundBlob {
      * @brief Constructs a batched blob from a vector of blobs
      * @details All passed blobs should meet following requirements:
      * - all blobs have equal tensor descriptors,
-     * - blobs layouts should be one of: NCHW, NHWC, NCDHW, NDHWC, NC, CN, C, CHW
-     * - batch dimensions should be equal to 1 or not defined (C, CHW).
+     * - blobs layouts should be one of: NCHW, NHWC, NCDHW, NDHWC, NC, CN, C, CHW, HWC
+     * - batch dimensions should be equal to 1 or not defined (C, CHW, HWC).
      * Resulting blob's tensor descriptor is constructed using tensor descriptors
      * of passed blobs by setting batch dimension to blobs.size()
      *

inference-engine/include/ie_input_info.hpp

@@ -70,6 +70,7 @@ class InputInfo {
      * NC - for 2-dimensional,
      * CHW - for 3-dimensional,
      * NCHW - for 4-dimensional
+     * NCDHW - for 5-dimensional
      * The default input layout might be changed preferred one using setLayout() function.
      * @return The precision used for input blob creation
      */

inference-engine/src/inference_engine/cnn_network_ngraph_impl.cpp

@@ -65,7 +65,7 @@ void CNNNetworkNGraphImpl::createDataForResult(const ::ngraph::Output<::ngraph::
         case 2:
             return l == Layout::CN || l == Layout::HW || l == Layout::NC;
         case 3:
-            return l == Layout::CHW;
+            return l == Layout::CHW || l == Layout::HWC;
         case 4:
             return l == Layout::NCHW || l == Layout::NHWC;
         case 5:

inference-engine/src/inference_engine/ie_compound_blob.cpp

@@ -259,6 +259,10 @@ TensorDesc verifyBatchedBlobInput(const std::vector<Blob::Ptr>& blobs) {
         blobLayout = NCHW;
         blobDims.insert(blobDims.begin(), blobs.size());
         break;
+    case HWC:
+        blobLayout = NHWC;
+        blobDims.insert(blobDims.begin(), blobs.size());
+        break;
     default:
         THROW_IE_EXCEPTION << "Unsupported sub-blobs layout - to be one of: [NCHW, NHWC, NCDHW, NDHWC, NC, CN, C, CHW]";
     }

inference-engine/src/inference_engine/ie_layouts.cpp

@@ -43,6 +43,8 @@ TensorDesc::TensorDesc(const Precision& precision, const SizeVector& dims, const
         case 3:
             if (blockingDesc.getOrder()[0] == 0 && blockingDesc.getOrder()[1] == 1 && blockingDesc.getOrder()[2] == 2) {
                 layout = Layout::CHW;
+            } else if (blockingDesc.getOrder()[0] == 1 && blockingDesc.getOrder()[1] == 2 && blockingDesc.getOrder()[2] == 0) {
+                layout = Layout::HWC;
             }
             break;
         case 4:
@@ -123,6 +125,7 @@ void TensorDesc::setLayout(Layout l) {
         inconsistentLayout = dims.size() != 4;
         break;
     case Layout::CHW:
+    case Layout::HWC:
         inconsistentLayout = dims.size() != 3;
         break;
     case Layout::CN:
@@ -319,6 +322,11 @@ BlockingDesc::BlockingDesc(const SizeVector& dims, Layout layout): offsetPadding
         l_order = {0, 1, 2};
         l_dims = dims;
         break;
+    case Layout::HWC:
+        checkDims(dims.size(), 3);
+        l_order = {1, 2, 0};
+        l_dims = dims;
+        break;
     case Layout::CN:
         checkDims(dims.size(), 2);
         l_order = {1, 0};

inference-engine/tests/unit/inference_engine/ie_blob_test.cpp

@@ -261,9 +261,12 @@ TEST_F(BlobTests, canMakeSharedBlob) {
             { InferenceEngine::Precision::FP32, size, InferenceEngine::CHW });
     InferenceEngine::TBlob<float>::Ptr blob3
             = InferenceEngine::make_shared_blob<float>({ InferenceEngine::Precision::FP32, { 0 }, InferenceEngine::C });
+    InferenceEngine::TBlob<float>::Ptr blob4 = InferenceEngine::make_shared_blob<float>(
+            { InferenceEngine::Precision::FP32, size, InferenceEngine::HWC });
     ASSERT_EQ(blob1->size(), 0);
     ASSERT_EQ(blob2->size(), 1);
     ASSERT_EQ(blob3->size(), 0);
+    ASSERT_EQ(blob4->size(), 1);
 }
 
 TEST_F(BlobTests, cannotCreateBlobWithIncorrectPrecision) {