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[CPU] Drop redundant MemoryOutput nodes #27189
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ov::test::utils::compare(tx_result, tx_result_ref, 1e-4, 1e-4); | ||
ov::test::utils::compare(tz_result, tz_result_ref, 1e-4, 1e-4); | ||
} |
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Maybe we also need to add check if exist MemoryOutput in compiledModel.
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Yes, for sure, but this is a common test, therefore we cannot add plugin specific checks there. To test the topology we have to introduce a dedicated CPU SL test, and I'm going to do this soon.
if (Type::MemoryOutput == childNode->getType()) { | ||
if (MemoryOutput && MemoryOutput != childNode) { | ||
//only one child MemoryOutput is expected | ||
return false; | ||
} | ||
MemoryOutput = childNode; | ||
} |
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Is it possible there is a case that ReadValue follows 2 Assginns, only 1 Assgin have same variable ID with current ReadValue?
If yes, I suggest only check if exist ReadValue follow Assgin with same Variable Id. What's your idea?
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Probably it does make sense, you're right. I will extend the condition.
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Done
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the changes in the template plugin LGTM
@xipingyan , do you have any further comments? |
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LGTM
@dmitry-gorokhov , the PR is ready for the final review. |
### Details: In direct ReadValue->Assign pairs the Assign node is practically useless as there are no other layers that might modify data in between. Therefore, it does make sense to remove corresponding MemoryOutput nodes to eliminate additional overheads on their processing. ### Tickets: - CVS-153035 - CVS-155112
### Details: - *New `ReadValueWithSubgraph` node.* - *Move `ReadValue`'s initial subgraph nodes to `ReadValueWithSubgraph`* - *Mirror `ReadValueWithSubgraph `to `MemoryInput`* - *Upgrade MemoryInput and MemoryInputBase in order to let them support multiple inputs" - *Call new interface `Init` and `Activate` of ov::intel_cpu::Graph, avoid to memory copy. Refer: #25385 - *Depends on #27189 ### Tickets: - *128743* --------- Signed-off-by: xipingya <[email protected]> Co-authored-by: Egor Duplensky <[email protected]> Co-authored-by: Maksim Kutakov <[email protected]> Co-authored-by: Maksim Kutakov <[email protected]>
Details:
In direct ReadValue->Assign pairs the Assign node is practically useless as there are no other layers that might modify data in between. Therefore, it does make sense to remove corresponding MemoryOutput nodes to eliminate additional overheads on their processing.
Tickets: