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Feature/antonvor/onednnv2.4.4 migration clean #98

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wants to merge 101 commits into from
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Feature/antonvor/onednnv2.4.4 migration clean #98

wants to merge 101 commits into from

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antonvor
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nivas-x86 and others added 30 commits December 10, 2021 21:58
@nivas-x86 @antonvor
x64: jit reorder: do not allow excess padded dim
bb35c78
@AlexPeskov @antonvor
jit: avx512: conv: Fix missed ur_w iteration
5f9c6d9 
Signed-off-by: Alexander Peskov <[email protected]>
@dmitry-gorokhov @antonvor
Enable jit sse41 NxN convolution for grayscale input
3d31d4e
@AlexPeskov @antonvor
Support of strided blobs for [de]convolution
35c5c4d
@dmitry-gorokhov @antonvor
Updated sse41 jit convolutions to support padded channels
f2f9116
@dmitry-gorokhov @antonvor
Added missed optimized reorder cases
9eb3b52
@dmitry-gorokhov @antonvor
Introduced Depthwise and Quantization post ops
6c08157 
Primitives that supports new post ops:
- Jit Convolutions (FP32,BF16,INT8)
- Jit,Ref Pooling (INT8)
@AlexPeskov @antonvor
Pooling pads like Caffe
83004aa 
Signed-off-by: Alexander Peskov <[email protected]>

Signed-off-by: Alexander Peskov <[email protected]>
@alexey-varyzgin @antonvor
TBB_AUTO was enabled
60fc886
@AlexPeskov @antonvor
Add API function dnnl_memory_set_data_handle_no_pads_proc
4d181b7 
Allow to set data handler without padding processing.

Signed-off-by: Alexander Peskov <[email protected]>
@alexey-varyzgin @antonvor
nchw_pooling dense fix
79946a0
@dmitry-gorokhov @antonvor
Enabled BWD (JIT/GEMM) FP32 Convoltions + Depthwise post ops fusings
93fb75a
@ilya-lavrenov @antonvor
Fixes for MKLDNN to enable LTO
06b4fd5
@antonvor
[MSVC] Enabling SIMD functionality for VS2019
dc4929c
@alexey-varyzgin @antonvor
Included BF16 Gemm into public API
307465c 
Signed-off-by: Alexander Peskov <[email protected]>
@AlexPeskov @antonvor
Avoid usage of undefined macro
936f9c5 
Signed-off-by: Alexander Peskov <[email protected]>
@AlexPeskov @antonvor
Fixed undef warnings
f71cad0 
Signed-off-by: Alexander Peskov <[email protected]>

Signed-off-by: Alexander Peskov <[email protected]>
@AlexPeskov @antonvor
Add several uni instruction wrappers into jit_generator
5626b9c
@AlexPeskov @antonvor
Relaxed mb strides check for FP32/BF16 Convolutions
7534b48
@AlexPeskov @antonvor
Fix ODR violation
2cdfd44 
Signed-off-by: Alexander Peskov <[email protected]>
@AlexPeskov @antonvor
fix name matching with system strauct 'user' in llvm-android toolchain
702e52f 
Signed-off-by: Alexander Peskov <[email protected]>
@dmitry-gorokhov @antonvor
Added JIT FP32 Softmax for arbitrary inner_size
62bc011 
[WA] Disabled custom JIT Softmax for ndims == 3
@a-sidorova @antonvor
Added support of hsigmoid, round_half_to_even, round_half_away_from_z…
8f39a9c 
…ero elementwise algorithms
@dmitry-gorokhov @antonvor
Limit applicability of is_1stconv logic for JIT FP32/BF16 AVX512 Conv…
1d89661 
…olution
@dmitry-gorokhov @antonvor
[WA] Removed kernel_outside_src condition on JIT FP32/BF16 Convolutions
d592713
@dmitry-gorokhov @antonvor
Added custom vesrion of JIT DW FP32 Convolution with 5D input support
6357a4f
@dmitry-gorokhov @antonvor
Asymmetric quntization for activations
8acabd7
@dmitry-gorokhov @antonvor
Added 3D DW case support for JIT INT8 Convolutions
8f48f6a
@dmitry-gorokhov @antonvor
[WA] Disabled weights md transpose in FC to prevent perf degradations
28fcba3
@dmitry-gorokhov @antonvor
Added fork version of JIT BF16 DW Convolution
dffbab5
antonvor and others added 26 commits December 10, 2021 21:59
@antonvor
ref pooling: perf fix
d2298d2
@antonvor
avx512: fixed prelu binary post op
7c19be8
@antonvor
perf fixes for quantization post ops
d9d2858
@antonvor
jit_avx512_core_x8s8s32x_deconvolution: fixed vmm indexes for quantiz…
731d413 
…ation post op
@antonvor
todo: fix assert(idx < max_idx)
7f7ab67
@antonvor
simple reorder: temporarily disabled zero padding
4d637f1
@antonvor
ref nchw pooling perf fix
582f92e
@vladislav-volkov @antonvor
OneDNN selective build
7136a44
@antonvor
Disable unused primitives
2687c30
@antonvor
Fetch few reorder fixes from most recent oneDNN
fdcdaac
@antonvor
Fix possible data race when accessing global reorder list
064e50e
@alexey-varyzgin @antonvor
Brgemm implementation has perf degradation in RNN node
0f3826a
@antonvor
Enable matmul primitives
c01be0f
@antonvor
fixed is_accepted_postop check in jit_uni_postops_injector.cpp for de…
66777d6 
…pthwise and quantization post ops
@antonvor
temporarily disabled oneDNN original dw conv fusing
dd5bcef
@antonvor
reverted old behavior with pdim_consistent check due to perf problems
b380bfb
@antonvor
WIP: reverted old behavior for post ops injector to fix accuracy issu…
5a621de 
…es with depthwise and quantization post ops
@maxnick @antonvor
Dyn batch hadling to some convolutions and mem desc comparison restri…
a0e3f1a 
…cted
@dmitry-gorokhov @antonvor
Enabled AMX primitives
260ef72
@dmitry-gorokhov @antonvor
AMX primitives: explicilty pass dst_type into has_default_values checks
9f3c211
@dmitry-gorokhov @antonvor
Extended int8 AMX convolutions to support depthwise/quantization post…
4e08cb4 
… ops
@dmitry-gorokhov @antonvor
Renamed matmul kernel type: brg -> brgemm
594c9fa
@dmitry-gorokhov @antonvor
Fixed bias addition order in brgemm kernel
ffa9549
@xuchen-intel @antonvor
Add several unified instructions
d773239
@alexey-varyzgin @antonvor
[1D] Enlarge support
f8478d3
@antonvor
Update uni_ jit methods to avoid mixing vex and nonVEX instructions
7930a05
@antonvor antonvor self-assigned this Dec 10, 2021
@antonvor antonvor mentioned this pull request Dec 10, 2021
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@dmitry-gorokhov
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Merged as part of #104

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