added this months Nov 22 reports

TGs/verification-task-group/projects/ARVM-FunctionalCoverage/meetings/2022/monthly-report-2022-Nov-21.md

@@ -0,0 +1,50 @@
+
+[comment]: # "this template is for ARVM projects"
+
+# **ARVM-FunctionalCoverage** Monthly Report for 21-November-2022
+
+Project leader : Simon Davidmann   
+Lead company :  Imperas  
+Participating companies : SiLabs, Dolphin  
+
+## Overview
+There are almost 1,000 instructions in RV64 (inc. all ratified and soon to be ratified extensions).  
+For each instruction somebody will need to write SystemVerilog covergroups and coverpoints…   
+Maybe 10-40 lines of SystemVerilog for each instruction…   
+That is 10,000-40,000 lines of SystemVerilog code to be written… (and be correct and working…)  
+And that is just for the basic un-privilege mode ISA…   
+
+This sub-project is to enable the developing of open-source VIPs (such as functional coverage) that can be used for many different core configurations/implementations.  
+
+## Current Status
+Initial focus is F,Zfinx (FPU) functional coverage for cv32e40pv2 (Dolphin) and Zc for cv32e40s (SiLabs).   
+
+cv32e40p used first generation of SystemVerilog for RV32I generated by Imperas in 2020.  
+Second generation architecture is generated and works directly from RVVI-TRACE core tracer testbench interface.   
+
+Uses machine readable ISA definition and generates examples as compliance level functional coverage for RV32I, RV32M.   
+Currently soliciting input / requirements on what needs to be covered in verification plans for different ISA extensions.   
+
+Also, beta code generated for many extensions, including: 32 bit I, E, M, C, B, K.  237 instructions covered in 2030 coverpoints.  
+
+## Key activities / tasks completed this month
+- OpenHW TV S03/E08 - Advancing RISC-V Processor Verification https://www.youtube.com/watch?v=2CHzsKsFU0s
+    - Mike Thompson, Simon Davidmann, Pete Lewin (Imagination), Rupert Baines (Codasip)
+    - subject included some of the new projects, e.g. ARVM-Standards, ARVM-TestbenchQuality, and this project: **ARVM-FunctionalCoverage**
+- F,Zfinx (FPU): First SystemVerilog functional coverage code for FPU has been generated and feedback from Dolphin has meant many more cross coverage and fixed values have been included
+- Zc (code-size-reduction): has been coded up and generated coverage is being reviewed by SiLabs - with feedback on cross coverage - and requirements for interrupt coverage across muli-cylce inctructions like push/pop/mv  
+- output of code generator has sections for verification plan in .csv - currently being reviewed  
+- output also .md files of summaries of each extension
+
+## Planned activities / tasks for coming month
+- reviews of resultant functional coverage (RV32I, RV32M, F, Zc)   
+- addition of more requirements for F and Zc
+- complete interrupt coverage over multi-cycle instructions  
+- addition of more design verification (DV) coverage such as hazards (and micro-architectural)   
+- scheduling of regular sub-project progress meetings (currently they are ad-hoc)  
+- discussions regarding working with isacov
+
+## Issues / items that are slowing progress
+- none - just starting up...
+
+

TGs/verification-task-group/projects/ARVM-SoCIntegration/meetings/2022/monthly-report-2022-Nov-21.md

@@ -0,0 +1,38 @@
+
+[comment]: # "this template is for ARVM projects"
+
+# **ARVM-SocIntegration** Monthly Report for 21-November-2022
+
+Project leader : Simon Davidmann   
+Lead company :  Imperas  
+Participating companies : (initial discussions with non-member Breker)
+
+## Overview
+To consider requirements and solutions for SoC core integration verification (for example cache coherency with uncore components)
+
+## Current Status
+Starting to have discussion on graph based test program generation like PSS and Breker
+
+Current view:  
+There are several levels of verification (read from bottom):
+- SoC integration level - verifying the integration of the core IP - SoC level integration test
+- core DV level - verifying at micro-architecture level - is the implementation good
+- core compliance level - basically ISA - has the spec been understood - verifying architecture understanding  
+
+## Key activities / tasks completed this month
+- had initial discussions 
+
+Still early days - just starting to collect information  
+
+
+## Planned activities / tasks for coming month
+- Imperas and Breker(currently non-member of OpenHW) have paper at RISC-V Summit in Dec. 
+    - "The New Verification Ecosystem that Supports RISC-V Verification for all Adopters."
+
+## Issues / items that are slowing progress
+- none - just starting up...
+
+## Other information
+
+
+

TGs/verification-task-group/projects/ARVM-Standards/meetings/2022/monthly-report-2022-Nov-21.md

@@ -0,0 +1,36 @@
+
+[comment]: # "this template is for ARVM projects"
+
+# **ARVM-Standards** Monthly Report for 21-November-2022
+
+Project leader : Simon Davidmann   
+Lead company :  Imperas  
+Participating companies : OpenHW, SiLabs, Dolphin, NXP, Intrinsix 
+
+## Overview
+Defining and implementing evolving interface standards for test bench components to enable better test bench component reuse and potentially stimulate availability of compatible VIPs.  
+Easing the adoption of interface to core tracer and test bench (RVVI-TRACE).  
+Easing the adoption interface of test bench to Verification IP that includes the reference model (RVVI-API).  
+Enabling the development of other interfaces, e.g. RVVI-VVP Virtual Verification Peripherals.   
+
+## Current Status
+Within OpenHW core verification projects, RVVI-TRACE and RVVI-API are in use in cv32e40x and cv32e40s core-v-verif testbenches to allow use of Imperas async-lock-step-compare VIPs.  
+This month has seen RVVI just now starting to be used in cv32e40s.  
+Existing test benches use ad-hoc virtual peripherals.  
+
+## Key activities / tasks completed this month
+- SiLabs, OpenHW, Imperas migrated cv32e40s test bench from ad-hoc to RVVI-TRACE and RVVI-API
+- with this integration made several requests for enhancements to RVVI
+
+## Planned activities / tasks for coming month
+- port cv32e40pv2 core-v-verif test bench from ad-hoc to use of RVVI
+- discussions with RISC-V International compliance group on RVVI-VVP (Virtual Peripherals) (collaborative paper accepted for RISC-V summit in Dec.)
+- arrange OpenHW discussions on RVVI-VVP   
+    the existing testbench approach of ad hoc interrupts is starting to become hard to understand and use -  
+        "Disjoint control of Interrupt interface in CORE-V-VERIF"     https://github.com/openhwgroup/core-v-verif/issues/1499
+    -  illustrating that standardization will be more efficient...     
+
+## Issues / items that are slowing progress
+- none - just starting up...
+
+

TGs/verification-task-group/projects/ARVM-TestbenchQuality/meetings/2022/monthly-report-2022-Nov-21.md

@@ -0,0 +1,34 @@
+
+[comment]: # "this template is for ARVM projects"
+
+# **ARVM-TestbenchQuality** Monthly Report for 21-November-2022
+
+Project leader : Simon Davidmann   
+Lead company :  Imperas  
+Participating companies : Codasip
+
+## Overview
+Developing quality measurement of test benches - so quality of cores can be predicted (for example defining fault models and tests and relating those to TRL levels)  
+
+## Current Status
+Currently have TRL   
+Has been discussion on MatterMost on what TRLs and verification sign-off actually means and how quantifiable different items should be...  
+Belief is that people are strong advocates for quantitative metrics.  
+
+## Key activities / tasks completed this month
+- reviewed TRL slides (https://docs.google.com/presentation/d/1XrhbHpFRYtAiSvAMPhf7b5oIIrpJKBIv/edit#slide=id.p1)  
+
+Still early days - just starting to collect information  
+
+
+## Planned activities / tasks for coming month
+- arrange first OpenHW discussions  
+
+## Issues / items that are slowing progress
+- none - just starting up...
+
+## Other information
+- 2021 12min YouTube Video on ["Better Quality RTL"](https://www.youtube.com/watch?v=wwSEIEfxysc) from Philippe Luc of Codasip 
+
+
+

TGs/verification-task-group/projects/CV32E20/meetings/2022/VTG monthly-report-2022-Nov-21.md

@@ -0,0 +1,43 @@
+
+[comment]: # "this template is for core verification projects"
+
+# **CV32E20 (CVE2)** Monthly Report for 21-November-2022  
+
+## Overview  
+Targeted core : CV32E20  
+Verification project leader :   Shared responsibility Maarten Arts / Lee Hoff  
+Lead company : NXP / Intrinsix  
+Target date verification complete (RTL Freeze) :  2023-Q2  
+Target verification quality level (TRL 1-5) :    TRL5  
+Verification approach being used (self check, compare signature, compare trace file, lock-step-compare, other) :   step & Compare  
+Reference model used (Imperas, spike, spike-modified, qemu, qemu-modified, other) :   Imperas  
+Test Generator used (riscv-dv, Valtrix, force-riscv, other) :  riscv-dv(?)  
+Formal approach (Jasper, Questa formal, Onespin, other) : not determined, but Jasper as preferred tool  
+
+## Current Status  
+Core revision version being tested : 0.1  
+Core specification (link to pdf) :   https://ibex-core.readthedocs.io/en/latest/ (but needs to be ported to CV32E20)  
+Verification plan / specification completeness (%) :  0%  
+Test bench (link GitHub) :   Being worked on  
+Functional coverage code created completeness (%) :  0%  
+Formal / simulation assertions written completeness (%) :   0%  
+
+## Key activities / tasks completed this month  
+- Stood up "Hello World in core-v-verif"  
+- RTL changes to database  
+
+## Planned activities / tasks for coming month  
+- Complete project planning  
+- Continue verification stand up  
+- Submit Plan Approval (PA) gate in December  
+
+## Issues / items that are slowing progress  
+- tbd    
+
+## Risks
+- to project timescales    
+	-- tbd    
+- to project quality    
+	-- tbd    
+
+#

TGs/verification-task-group/projects/CV32E40P_v2/README.md

@@ -1 +1 @@
-Presentations related to the development of v2.0.0 of the CV32E40P.
+Information and Presentations related to the development of v2.0.0 of the CV32E40P.

TGs/verification-task-group/projects/CV32E40P_v2/meetings/2022/monthly-report-2022-11-21.md

@@ -0,0 +1,49 @@
+
+[comment]: # "this template is for core verification projects"
+
+# **CV32E40Pv2** Monthly Report for 21-November-2022
+
+## Overview
+Targeted core : CV32E40P  
+Verification project leader : Xavier Aubert  
+Lead company : Dolphin Design  
+Target date verification complete (RTL Freeze) : 2023-03  
+Target verification quality level (TRL 1-5) : 5  
+Verification approach being used (self check, compare signature, compare trace file, lock-step-compare, other) : lock-step-compare  
+Reference model used (Imperas, spike, spike-modified, qemu, qemu-modified, other) : Imperas  
+Test Generator used (riscv-dv, Valtrix, force-riscv, other) : riscv-dv  
+Formal approach (Jasper, Questa formal, Onespin, other) : OneSpin with RISC-V app for IMCFZfinxZicsrZicountZifencei + X  
+
+## Current Status
+Core revision version being tested : v2  
+Core specification (link to pdf) :  [cv32e40p_v1.1.0](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/cv32e40p_v1.1.0/)  
+Verification plan / Formal Verification Plan / specification completeness (%) : 10 / 15 / 60  
+Test bench (link GitHub) : [core-v-verif](https://core-v-verif-verification-strategy.readthedocs.io/en/latest/cv32_env.html#core-scoreboard)  
+Functional coverage code created completeness (%) : 0  
+Formal / Simulation assertions written completeness (%) : 100 / 0  
+
+## Key activities / tasks completed this month
+- First version of specification available (cv32e40p_v1.1.0)  
+- Test-bench moving to RVFI support: Interrupts OK, some work still needed (Debug feature, ...)  
+- First toolchain has been delivered (elw, simd8-16)  
+- Checked and corrected the corev-dv generation of xcorev2p0 instructions in assembly available to date.  
+- Continue debugging/correcting the bugs found by Formal Verification.  
+- Formal Verification working with FPU instructions latency.  
+- Started Simulation and Formal Verification Plans  
+
+## Planned activities / tasks for coming month
+- Continue with specification updates (HWLoops constraints, FPU...).  
+- Continue to debug/correct the bugs found by Formal Verification.  
+- Full unbounded Formal Verification runs on-going since 3weeks (80% done)  
+- Continue Verification Plans.  
+
+## Issues / items that are slowing progress
+- Documentation generation with changelog and versioning.  
+- OpenHW staff support seems not as responsive on E40P as on other projects (E40X/S, CVA6...).  
+- Run-time for formal verification due to multiple configurations  
+
+## Risks
+- to project timescales  
+None up to now.  
+
+#

TGs/verification-task-group/projects/CV32E40S/meetings/2022/monthly-report-2022-Nov-21.md

@@ -0,0 +1,69 @@
+
+# cv32e40s Monthly Report for 21-November-2022
+
+## Overview
+Targeted core : cv32e40s  (The X is not being worked on because we are working on the S)  
+Verification project leader : Henrik Fegran  
+Lead company : Silicon Labs  
+Target date verification complete (RTL Freeze) : 2023 Q1/Q2  
+Target verification quality level (TRL 1-5) : TRL5  
+Verification approach being used (self check, compare signature, compare trace file, lock-step-compare, other) :
+- Self-checking directed tests
+- non-self-checking directed tests
+- constrained random
+- asserts
+- formal verification
+- ...   
+
+Reference model used (Imperas, spike, spike-modified, qemu, qemu-modified, other) : Imperas  
+Test Generator used (riscv-dv, Valtrix, force-riscv, other) : riscv-dv  
+Formal approach (Jasper, Questa formal, Onespin, other) : Jasper  
+
+## Current Status
+Core revision version being tested : 0.6.0  
+Core specification (link to pdf) : https://docs.openhwgroup.org/_/downloads/cv32e40s-user-manual/en/latest/pdf/  
+Verification plan / specification completeness (%) : 95%  
+Test bench (link GitHub) : https://github.com/openhwgroup/core-v-verif/tree/cv32e40s/dev  
+Functional coverage code created completeness (%) : 80%  
+Formal / simulation assertions written completeness (%) :  90%  
+
+## Key activities / tasks completed this month
+- vPlans  
+	-- vPlan updates  (Zb, Debug)  
+	-- Link to coverage  (PMP, Fencei, Umode)  (Revealed some holes)  
+- Xsecure  
+	-- Xsecure directed tests  
+	-- Xsecure more assertions  
+- CLIC  
+	-- Directed test (for CLIC-related CSRs)  
+- ISS  
+	-- ImperasDV port to 40s  (new impdv infrastructure)  
+	-- CLIC enable support through ImperasDV  
+- Misc  
+	-- Fix OBI if params  (Big UVM undertaking to support parameterized interfaces)  
+	-- User-mode functional coverage  
+
+## Planned activities / tasks for coming month
+- OBI 1.5 support in core-v-verif  
+- Debug testing updated to 1.0.0 spec  (easier said than done)  
+- Link to coverage in vplans  
+- Xsecure, bus hardening asserts  
+- Riscv-DV, support for CLIC and Zc  
+
+## Other activities
+- Formal testbench in core-v-verif working again for 40s  
+	-- Mike has shown interest in contributing  
+	-- Roadmap https://github.com/openhwgroup/core-v-verif/issues/1459  
+- RVFI asserts started  (not written to be generalizable, not competing with riscv_formal)  
+
+## Issues / items that are slowing progress
+- Switch to new ImperasDV ISS framework  
+	-- Have unreliable regressions, don't know what the real projected bug-fixing effort is  
+
+## Risks
+- to project timescales    
+	-- Thoroughness of the vplans  (extremely meticulous and ambitious at times)  
+	-- Unwritten asserts/covers/tests  
+	-- Coverage not hit  
+- to project quality    
+	-- Riscof  

TGs/verification-task-group/projects/CV32E40X/meetings/2022/monthly-report-2022-Nov-21.md

@@ -0,0 +1,17 @@
+
+[comment]: # "this template is for core verification projects"
+
+# CV32E40X Monthly Report for 21-November-2022
+
+## Overview
+Targeted core :  CV32E40SX  
+Verification project leader : Henrik Fegran  
+Lead company :  Silicon Laboratories Inc.  
+
+
+## Notes
+- Silicon Labs is focusing verification on CV32E40S at the current point in time.   
+The overlap between E40S and E40X is large, and thus little work is being done directly on the E40X core at the moment.   
+Due to this, we will not be providing separate updates for that core for now.  
+
+#