openhwgroup · MikeOpenHWGroup · Oct 21, 2022 · Mar 11, 2022 · Mar 11, 2022 · May 30, 2022
diff --git a/OpenHW-Presentations/2021-06-29-Presentations/CORE-V-MCU Roadmap-v2.pdf b/OpenHW-Presentations/2021-06-29-Presentations/CORE-V-MCU Roadmap-v2.pdf
diff --git a/OpenHW-Presentations/2021-06-29-Presentations/CORE-V_Roadmap_Futurewei.pdf b/OpenHW-Presentations/2021-06-29-Presentations/CORE-V_Roadmap_Futurewei.pdf
diff --git a/OpenHW-Presentations/2021-06-29-Presentations/OpenHW-Group-Overview-2021-06-29 2021.pdf b/OpenHW-Presentations/2021-06-29-Presentations/OpenHW-Group-Overview-2021-06-29 2021.pdf
diff --git a/OpenHW-Presentations/2021-06-29-Presentations/OpenHW_Futurewei_Verification(2021-06-28).pdf b/OpenHW-Presentations/2021-06-29-Presentations/OpenHW_Futurewei_Verification(2021-06-28).pdf
diff --git a/OpenHW-Presentations/2021-06-29-Presentations/core-v-sw-roadmap-futurewei-29-jun-2021.pdf b/OpenHW-Presentations/2021-06-29-Presentations/core-v-sw-roadmap-futurewei-29-jun-2021.pdf
diff --git a/...enHW-Project-Concept-Proposal.(PASSED).md → ...enHW-Project-Concept-Proposal.(PASSED).md b/...enHW-Project-Concept-Proposal.(PASSED).md → ...enHW-Project-Concept-Proposal.(PASSED).md
diff --git a/...ns-and-Plans/CORE-V-CVA5/PC-Taiga-CVA5.md → ...ns-and-Plans/CORE-V-CVA5/PC-Taiga-CVA5.md b/...ns-and-Plans/CORE-V-CVA5/PC-Taiga-CVA5.md → ...ns-and-Plans/CORE-V-CVA5/PC-Taiga-CVA5.md
diff --git a/...iga_formal_overview_openhw-2021-28jun.pdf → ...iga_formal_overview_openhw-2021-28jun.pdf b/...iga_formal_overview_openhw-2021-28jun.pdf → ...iga_formal_overview_openhw-2021-28jun.pdf
diff --git a/...ga_formal_overview_openhw-2021-28jun2.pdf → ...ga_formal_overview_openhw-2021-28jun2.pdf b/...ga_formal_overview_openhw-2021-28jun2.pdf → ...ga_formal_overview_openhw-2021-28jun2.pdf
diff --git a/.../CORE-V-GNU-Tools/core-v-gnu-tools-ppl.md → .../CORE-V-GNU-Tools/core-v-gnu-tools-ppl.md b/.../CORE-V-GNU-Tools/core-v-gnu-tools-ppl.md → .../CORE-V-GNU-Tools/core-v-gnu-tools-ppl.md
diff --git a/...s-and-Plans/CORE-V-HAL/HAL-diagram-PC.png → ...s-and-Plans/CORE-V-HAL/HAL-diagram-PC.png b/...s-and-Plans/CORE-V-HAL/HAL-diagram-PC.png → ...s-and-Plans/CORE-V-HAL/HAL-diagram-PC.png
diff --git a/...action-Layer-HAL-Requirements-for-PC.pptx → ...action-Layer-HAL-Requirements-for-PC.pptx b/...action-Layer-HAL-Requirements-for-PC.pptx → ...action-Layer-HAL-Requirements-for-PC.pptx
diff --git a/...d-Plans/CORE-V-HAL/Project-Concept-HAL.md → ...d-Plans/CORE-V-HAL/Project-Concept-HAL.md b/...d-Plans/CORE-V-HAL/Project-Concept-HAL.md → ...d-Plans/CORE-V-HAL/Project-Concept-HAL.md
diff --git a/...CORE-V-IDE-prelminary-project-proposal.md → ...CORE-V-IDE-prelminary-project-proposal.md b/...CORE-V-IDE-prelminary-project-proposal.md → ...CORE-V-IDE-prelminary-project-proposal.md
diff --git a/...20523-OHG-ProjectConcept-CEA_L1_Dcache.md → ...20523-OHG-ProjectConcept-CEA_L1_Dcache.md b/...20523-OHG-ProjectConcept-CEA_L1_Dcache.md → ...20523-OHG-ProjectConcept-CEA_L1_Dcache.md
diff --git a/...ORE-V_DEV-KIT_project_concept_approved.md → ...ORE-V_DEV-KIT_project_concept_approved.md b/...ORE-V_DEV-KIT_project_concept_approved.md → ...ORE-V_DEV-KIT_project_concept_approved.md
diff --git a/...and-Plans/CORE-V-MCU-SoC/Arnold2-arch.png → ...and-Plans/CORE-V-MCU-SoC/Arnold2-arch.png b/...and-Plans/CORE-V-MCU-SoC/Arnold2-arch.png → ...and-Plans/CORE-V-MCU-SoC/Arnold2-arch.png
diff --git a/...C/CORE-V_MCU_Project_Plan_Nov10_2021.xlsx → ...C/CORE-V_MCU_Project_Plan_Nov10_2021.xlsx b/...C/CORE-V_MCU_Project_Plan_Nov10_2021.xlsx → ...C/CORE-V_MCU_Project_Plan_Nov10_2021.xlsx
diff --git a/...C/CORE-V_MCU_Project_Plan_Oct27_2021.xlsx → ...C/CORE-V_MCU_Project_Plan_Oct27_2021.xlsx b/...C/CORE-V_MCU_Project_Plan_Oct27_2021.xlsx → ...C/CORE-V_MCU_Project_Plan_Oct27_2021.xlsx
diff --git a/...ns/CORE-V-MCU-SoC/Core-V-MCU-SoC-Plan.pod → ...ns/CORE-V-MCU-SoC/Core-V-MCU-SoC-Plan.pod b/...ns/CORE-V-MCU-SoC/Core-V-MCU-SoC-Plan.pod → ...ns/CORE-V-MCU-SoC/Core-V-MCU-SoC-Plan.pod
diff --git a/...d-Plans/CORE-V-MCU-SoC/MCU-PL-Document.md → ...d-Plans/CORE-V-MCU-SoC/MCU-PL-Document.md b/...d-Plans/CORE-V-MCU-SoC/MCU-PL-Document.md → ...d-Plans/CORE-V-MCU-SoC/MCU-PL-Document.md
diff --git a/...V-MCU-SoC/MCU-SoC-Project-Plan-at-PL.xlsx → ...V-MCU-SoC/MCU-SoC-Project-Plan-at-PL.xlsx b/...V-MCU-SoC/MCU-SoC-Project-Plan-at-PL.xlsx → ...V-MCU-SoC/MCU-SoC-Project-Plan-at-PL.xlsx
diff --git a/...CORE-V-MCU-SoC/PA-document-Oct-25-2021.md → ...CORE-V-MCU-SoC/PA-document-Oct-25-2021.md b/...CORE-V-MCU-SoC/PA-document-Oct-25-2021.md → ...CORE-V-MCU-SoC/PA-document-Oct-25-2021.md
diff --git a/...eliminary-project-proposal-for-MCU-SoC.md → ...eliminary-project-proposal-for-MCU-SoC.md b/...eliminary-project-proposal-for-MCU-SoC.md → ...eliminary-project-proposal-for-MCU-SoC.md
diff --git a/...and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.png → ...and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.png b/...and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.png → ...and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.png
diff --git a/...nd-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.vsdx → ...nd-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.vsdx b/...nd-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.vsdx → ...nd-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.vsdx
diff --git a/...ans/CORE-V-MCU-UVM/MCU_UVM_Simplified.png → ...ans/CORE-V-MCU-UVM/MCU_UVM_Simplified.png b/...ans/CORE-V-MCU-UVM/MCU_UVM_Simplified.png → ...ans/CORE-V-MCU-UVM/MCU_UVM_Simplified.png
diff --git a/...ns/CORE-V-MCU-UVM/MCU_UVM_Simplified.vsdx → ...ns/CORE-V-MCU-UVM/MCU_UVM_Simplified.vsdx b/...ns/CORE-V-MCU-UVM/MCU_UVM_Simplified.vsdx → ...ns/CORE-V-MCU-UVM/MCU_UVM_Simplified.vsdx
diff --git a/...-MCU-UVM/TWG_Presentation_2022-01-24.pptx → ...-MCU-UVM/TWG_Presentation_2022-01-24.pptx b/...-MCU-UVM/TWG_Presentation_2022-01-24.pptx → ...-MCU-UVM/TWG_Presentation_2022-01-24.pptx
diff --git a/...CORE-V-MCU-UVM/mcu_uvm_project_concept.md → ...CORE-V-MCU-UVM/mcu_uvm_project_concept.md b/...CORE-V-MCU-UVM/mcu_uvm_project_concept.md → ...CORE-V-MCU-UVM/mcu_uvm_project_concept.md
diff --git a/...oposal for Core-V-VEC Research Project.md → ...oposal for Core-V-VEC Research Project.md b/...oposal for Core-V-VEC Research Project.md → ...oposal for Core-V-VEC Research Project.md
diff --git a/...V-X-IF/CV_X_Interface_project_concept.pdf → ...V-X-IF/CV_X_Interface_project_concept.pdf b/...V-X-IF/CV_X_Interface_project_concept.pdf → ...V-X-IF/CV_X_Interface_project_concept.pdf
diff --git a/...CV-X-IF/CV_X_Interface_project_launch.pdf → ...CV-X-IF/CV_X_Interface_project_launch.pdf b/...CV-X-IF/CV_X_Interface_project_launch.pdf → ...CV-X-IF/CV_X_Interface_project_launch.pdf
diff --git a/...d-Plans/CV-X-IF/TWG-2021-06-28_cvxif.pptx → ...d-Plans/CV-X-IF/TWG-2021-06-28_cvxif.pptx b/...d-Plans/CV-X-IF/TWG-2021-06-28_cvxif.pptx → ...d-Plans/CV-X-IF/TWG-2021-06-28_cvxif.pptx
diff --git a/...2E40Pv2-Project-Concept-June-28-2021.pptx → ...2E40Pv2-Project-Concept-June-28-2021.pptx b/...2E40Pv2-Project-Concept-June-28-2021.pptx → ...2E40Pv2-Project-Concept-June-28-2021.pptx
diff --git a/...V32E40Pv2-Project-Launch-Nov-22-2021.pptx → ...V32E40Pv2-Project-Launch-Nov-22-2021.pptx b/...V32E40Pv2-Project-Launch-Nov-22-2021.pptx → ...V32E40Pv2-Project-Launch-Nov-22-2021.pptx
diff --git a/...V32E40Pv2-preliminary-project-proposal.md → ...V32E40Pv2-preliminary-project-proposal.md b/...V32E40Pv2-preliminary-project-proposal.md → ...V32E40Pv2-preliminary-project-proposal.md
@@ -1,131 +1,131 @@
-
-# OpenHW Preliminary Project Proposal: CV32E40P Second RTL Freeze (v2)
-
-## Summary of project
-
-This proposal is for a second RTL freeze or release of the CV32E40P, henceforth referred to as CV32E40Pv2. This release may include verification of additional parameter options, bug fixes, re-enabled RTL and/or new RTL and additional verification as required. This release should not remove features or otherwise break compatibility with the previous RTL freeze. Such changes should be reserved for the CV32E40 or a fork/variant.
-
-During initial development of the CV32E40P, some features were disabled, skipped, implemented in a minimal fashion or inadequately verified. Most notably, the PULP instructions were removed via a parameter. This was due to insufficient toolchain support and verification. The original intent of the CV32E40P is to include these PULP instructions as described in the [CV32E40* Features and Parameters](https://github.com/openhwgroup/core-v-docs/blob/master/cores/cv32e40p/CV32E40P_and%20CV32E40_Features_Parameters.pdf).
-
-What follows is a description of the different work items to be included in the CV32E40Pv2.
-
-### Add Selected PULP Extensions (Verification)
-
-These are the existing PULP instructions minus the bit manipulation (superseded by the draft B Extension) and SIMD (superseded by the draft P Extension).
-
-* Hardware loop (`Xcorevhwl`)
-* Multiply accumulate (`Xcorevmac`)
-* Post-increment and register-indexed load/store (`Xcorevpostinc`)
-* Direct branches (`Xcorevbi`)
-* General ALU operations (`Xvorevalu`)
-
-These instructions generally improve the power/performance point as well as reduce code size in selected applications, producing a core with compelling open source advantages.
-
-### Instruction Encoding (OPCODE) changes to align with RISC-V standard (RTL and Verification)
-
-As described in issue [#452](https://github.com/openhwgroup/cv32e40p/issues/452), the RTL needs to be updated to match RISC-V standard. Without correcting the instruction encodings to fit within the custom space defined by the RISC-V standard, the toolchain can't be completed, upstreamed and maintained.
-
-### Conversion to Draft Standard Extensions (RTL and Verification)
-
-The bit manipulation and SIMD PULP instructions are to be superseded by the draft B and P extensions respectively. Due to the overlap with the draft standard extensions as well as resource constraints, the CORE-V GNU compiler toolchain will not support these instructions. Without toolchain support these instructions cannot be verified or used by software. Due to the instruction encoding differences the PULP instructions in CV32E40Pv2 will not be binary compatible or supported by the existing PULP toolchain and therefore will not be usable for existing PULP users.
-
-For these reasons the existing instructions will be updated or replaced with draft standard compliant variants. This approach will keep the bit manipulation and SIMD features in the CV32E40P, albeit in a different form. Switching to the draft standard extension instructions will allow OpenHW to leverage existing toolchain support and modeling software for verification.
-
-####  Bit Manipulation (more important)
-Can be useful for e.g. cryptographic application
-
-#### SIMD
-Can be useful for signal processing
-
-### Debug Trigger Enhancement (RTL and Verification)
-
-Current debug trigger (hardware breakpoint) implementation only supports a single instruction breakpoint. The RISC-V Debug Specification provides a richer set of features like multiple breakpoints, data related breakpoints, etc.
-
-The debug trigger implementation should be extended with the following additional features:
-* Parameterizable number of breakpoints (such as 2 or 4 instead of 1)
-* Load/store address breakpoints (break when you access a certain memory address with a load/store instruction)
-* Option to configure the triggers to throw an exception instead of halting the core
-
-#### Debug Module (Documentation, RTL and Verification)
-
-The CV32E40P supports a a debug request input to place the core into debug mode.  The scope of the CV32E40P v2 could be expanded to include a Debug Module compliant with the RISC-V debug specification (v0.13.1 or higher).
-An obvious source for such a DM is the [PULP RISCV-dbg](https://github.com/pulp-platform/riscv-dbg) project.  Other implementation options are also available dependent upon member interest and contributions.
-
-The DM could be tighly integrated into CV32E40P v2 or loosely coupled.
-
-### FPU (RTL, Verification, Documentation)
-
-The CV32E40P has RTL to instantiate the FPU from the `fpnew` project from ETH. This project remains in the ETH GitHub. It is an implementation of the RISC-V standard FPU extension specification (F extension). It is not supported in the current version of the CV32E40P. The RTL may have become stale; however, the majority of the work will be in the verification and documentation.
-
-### Summary of Timeline
-
-To be checked
-
-## OpenHW Members/Participants committed to participate in CV32E40Pv2 project
-
-EM Microelectronic
-
-## Technical Project Leader(s) (TPLs)
-
-## Project Manager (PM)
-
-## Project Documents
-
-## Summary of requirements
-
-### Introduction
-
-### Initial project requirements
-
-### Future enhancements:
-
-
-## Explanation of why OpenHW should do this project
-
-## Industry landscape: description of competing, alternative, or related efforts in the industry
-
-### Related efforts to be described
-
-## External dependencies
-
-### Ownership of fpnew
-
-ETH owns this repository and we have not engaged with them to understand if OpenHW could take over support, to instantiate, fork, etc.
-
-### Ownership of ETH Debug Module
-
-ETH owns this repository but it is not active. We have not engaged with them to understand if OpenHW could take over support, to instantiate, fork, etc.
-
-## List of project outputs
-
-## TGs Impacted/Resource requirements
-
-## OpenHW engineering staff resource plan: requirement and availability
-
-## Engineering resource supplied by members - requirement and availability
-
-## OpenHW marketing resource - requirement and availability
-
-## Marketing resource supplied by members - requirement and availability
-
-## Funding supplied by OpenHW - requirement and availability
-
-## Funding supplied by members - requirement and availability
-
-## Architecture diagram
-
-## Who would make use of OpenHW output
-
-## Project license model
-
-
-## Description of initial code contribution, if required
-
-## Repository Structure
-
-## Project distribution model
-
-## Preliminary Project plan
-
-### Risk Register
-
+
+# OpenHW Preliminary Project Proposal: CV32E40P Second RTL Freeze (v2)
+
+## Summary of project
+
+This proposal is for a second RTL freeze or release of the CV32E40P, henceforth referred to as CV32E40Pv2. This release may include verification of additional parameter options, bug fixes, re-enabled RTL and/or new RTL and additional verification as required. This release should not remove features or otherwise break compatibility with the previous RTL freeze. Such changes should be reserved for the CV32E40 or a fork/variant.
+
+During initial development of the CV32E40P, some features were disabled, skipped, implemented in a minimal fashion or inadequately verified. Most notably, the PULP instructions were removed via a parameter. This was due to insufficient toolchain support and verification. The original intent of the CV32E40P is to include these PULP instructions as described in the [CV32E40* Features and Parameters](https://github.com/openhwgroup/core-v-docs/blob/master/cores/cv32e40p/CV32E40P_and%20CV32E40_Features_Parameters.pdf).
+
+What follows is a description of the different work items to be included in the CV32E40Pv2.
+
+### Add Selected PULP Extensions (Verification)
+
+These are the existing PULP instructions minus the bit manipulation (superseded by the draft B Extension) and SIMD (superseded by the draft P Extension).
+
+* Hardware loop (`Xcorevhwl`)
+* Multiply accumulate (`Xcorevmac`)
+* Post-increment and register-indexed load/store (`Xcorevpostinc`)
+* Direct branches (`Xcorevbi`)
+* General ALU operations (`Xvorevalu`)
+
+These instructions generally improve the power/performance point as well as reduce code size in selected applications, producing a core with compelling open source advantages.
+
+### Instruction Encoding (OPCODE) changes to align with RISC-V standard (RTL and Verification)
+
+As described in issue [#452](https://github.com/openhwgroup/cv32e40p/issues/452), the RTL needs to be updated to match RISC-V standard. Without correcting the instruction encodings to fit within the custom space defined by the RISC-V standard, the toolchain can't be completed, upstreamed and maintained.
+
+### Conversion to Draft Standard Extensions (RTL and Verification)
+
+The bit manipulation and SIMD PULP instructions are to be superseded by the draft B and P extensions respectively. Due to the overlap with the draft standard extensions as well as resource constraints, the CORE-V GNU compiler toolchain will not support these instructions. Without toolchain support these instructions cannot be verified or used by software. Due to the instruction encoding differences the PULP instructions in CV32E40Pv2 will not be binary compatible or supported by the existing PULP toolchain and therefore will not be usable for existing PULP users.
+
+For these reasons the existing instructions will be updated or replaced with draft standard compliant variants. This approach will keep the bit manipulation and SIMD features in the CV32E40P, albeit in a different form. Switching to the draft standard extension instructions will allow OpenHW to leverage existing toolchain support and modeling software for verification.
+
+####  Bit Manipulation (more important)
+Can be useful for e.g. cryptographic application
+
+#### SIMD
+Can be useful for signal processing
+
+### Debug Trigger Enhancement (RTL and Verification)
+
+Current debug trigger (hardware breakpoint) implementation only supports a single instruction breakpoint. The RISC-V Debug Specification provides a richer set of features like multiple breakpoints, data related breakpoints, etc.
+
+The debug trigger implementation should be extended with the following additional features:
+* Parameterizable number of breakpoints (such as 2 or 4 instead of 1)
+* Load/store address breakpoints (break when you access a certain memory address with a load/store instruction)
+* Option to configure the triggers to throw an exception instead of halting the core
+
+#### Debug Module (Documentation, RTL and Verification)
+
+The CV32E40P supports a a debug request input to place the core into debug mode.  The scope of the CV32E40P v2 could be expanded to include a Debug Module compliant with the RISC-V debug specification (v0.13.1 or higher).
+An obvious source for such a DM is the [PULP RISCV-dbg](https://github.com/pulp-platform/riscv-dbg) project.  Other implementation options are also available dependent upon member interest and contributions.
+
+The DM could be tighly integrated into CV32E40P v2 or loosely coupled.
+
+### FPU (RTL, Verification, Documentation)
+
+The CV32E40P has RTL to instantiate the FPU from the `fpnew` project from ETH. This project remains in the ETH GitHub. It is an implementation of the RISC-V standard FPU extension specification (F extension). It is not supported in the current version of the CV32E40P. The RTL may have become stale; however, the majority of the work will be in the verification and documentation.
+
+### Summary of Timeline
+
+To be checked
+
+## OpenHW Members/Participants committed to participate in CV32E40Pv2 project
+
+EM Microelectronic
+
+## Technical Project Leader(s) (TPLs)
+
+## Project Manager (PM)
+
+## Project Documents
+
+## Summary of requirements
+
+### Introduction
+
+### Initial project requirements
+
+### Future enhancements:
+
+
+## Explanation of why OpenHW should do this project
+
+## Industry landscape: description of competing, alternative, or related efforts in the industry
+
+### Related efforts to be described
+
+## External dependencies
+
+### Ownership of fpnew
+
+ETH owns this repository and we have not engaged with them to understand if OpenHW could take over support, to instantiate, fork, etc.
+
+### Ownership of ETH Debug Module
+
+ETH owns this repository but it is not active. We have not engaged with them to understand if OpenHW could take over support, to instantiate, fork, etc.
+
+## List of project outputs
+
+## TGs Impacted/Resource requirements
+
+## OpenHW engineering staff resource plan: requirement and availability
+
+## Engineering resource supplied by members - requirement and availability
+
+## OpenHW marketing resource - requirement and availability
+
+## Marketing resource supplied by members - requirement and availability
+
+## Funding supplied by OpenHW - requirement and availability
+
+## Funding supplied by members - requirement and availability
+
+## Architecture diagram
+
+## Who would make use of OpenHW output
+
+## Project license model
+
+
+## Description of initial code contribution, if required
+
+## Repository Structure
+
+## Project distribution model
+
+## Preliminary Project plan
+
+### Risk Register
+
diff --git a/...lans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx → ...lans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx b/...lans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx → ...lans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx