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Code style correction of cva6 #485

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whutddk
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@whutddk whutddk commented Jul 27, 2020

fix #477

Hello all, according to #477 , I have add prefixs "cva6_" to most of the RTL files, modules, and instantiation. So far, my tests only prove that the flow make fpga, which is for Genesys II is working properly. I will also test the other flow soon, because macro may block some bugs, which miss prefixs.


The mainly changes are as followed:

  • file name, module name, instantiation name
  • ariane -> cva6
  • riscv_pkg -> cva6_riscv_pkg
  • ariane_pkg -> cva6_pkg
  • std_cache_pkg -> cva6_std_cache_pkg
  • wt_cache_pkg -> cva6_wt_cache_pkg

The RTL codes in submodule are not modified, by the way.

@whutddk whutddk requested a review from zarubaf as a code owner July 27, 2020 13:48
Signed-off-by: Ruige Lee <[email protected]>
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Jbalkind commented Jul 28, 2020

Your modifications under the openpiton/ directory will break openpiton downstream. Please submit an appropriate PR to openpiton if you are going to change those filenames and interface wires.

Edit: To be clear, such a PR to OpenPiton should not change any OpenPiton module names or macro names. Simply the module instantiations and wire names that you have modified in this PR

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whutddk commented Jul 28, 2020

@Jbalkind Yes I understand, and modifying the code style is a huge job and easy to make mistakes. All related repositories should be changed at the same time to avoid errors. I will try to do that soon. And only after that, we can merge the PR.

Signed-off-by: Ruige Lee <[email protected]>
Signed-off-by: Ruige Lee <[email protected]>

# Conflicts:
#	src/cva6_mmu.sv
#	src/cva6_ptw.sv
#	src/frontend/cva6_instr_queue.sv
#	src/pmp/src/cva6_pmp.sv
#	src/pmp/src/cva6_pmp_entry.sv
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Prefixing of module names and file names
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