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fix #477
Hello all, according to #477 , I have add prefixs "cva6_" to most of the RTL files, modules, and instantiation. So far, my tests only prove that the flow
make fpga
, which is forGenesys II
is working properly. I will also test the other flow soon, because macro may block some bugs, which miss prefixs.The mainly changes are as followed:
The RTL codes in submodule are not modified, by the way.