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RTL correction for verilator (no added/removed lines). #952

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merged 1 commit into from
Feb 28, 2024
Merged

RTL correction for verilator (no added/removed lines). #952

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6 changes: 3 additions & 3 deletions rtl/cv32e40p_core.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1057,9 +1057,9 @@ module cv32e40p_core
assign csr_addr_int = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : '0);

// Floating-Point registers write
assign fregs_we = (FPU & !ZFINX) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) ||
(regfile_we_wb && regfile_waddr_fw_wb_o[5]))
: 1'b0;
assign fregs_we = (FPU == 1 & ZFINX == 0) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) ||
(regfile_we_wb && regfile_waddr_fw_wb_o[5]))
: 1'b0;

///////////////////////////
// ____ __ __ ____ //
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2 changes: 1 addition & 1 deletion rtl/cv32e40p_cs_registers.sv
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Expand Up @@ -509,7 +509,7 @@ module cv32e40p_cs_registers

// mimpid, Machine Implementation ID
CSR_MIMPID: begin
csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER) ? 32'h1 : 'b0;
csr_rdata_int = (FPU == 1 || COREV_PULP == 1 || COREV_CLUSTER == 1) ? 32'h1 : 'b0;
end

// unimplemented, read 0 CSRs
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8 changes: 4 additions & 4 deletions rtl/cv32e40p_ex_stage.sv
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Expand Up @@ -213,9 +213,9 @@ module cv32e40p_ex_stage
end
end else begin
regfile_alu_we_fw_o = regfile_alu_we_i & ~apu_en_i;
regfile_alu_we_fw_power_o = !COREV_PULP ? regfile_alu_we_i & ~apu_en_i :
regfile_alu_we_i & ~apu_en_i &
mult_ready & alu_ready & lsu_ready_ex_i;
regfile_alu_we_fw_power_o = (COREV_PULP == 0) ? regfile_alu_we_i & ~apu_en_i :
regfile_alu_we_i & ~apu_en_i &
mult_ready & alu_ready & lsu_ready_ex_i;
regfile_alu_waddr_fw_o = regfile_alu_waddr_i;
if (alu_en_i) regfile_alu_wdata_fw_o = alu_result;
if (mult_en_i) regfile_alu_wdata_fw_o = mult_result;
Expand All @@ -233,7 +233,7 @@ module cv32e40p_ex_stage

if (regfile_we_lsu) begin
regfile_we_wb_o = 1'b1;
regfile_we_wb_power_o = !COREV_PULP ? 1'b1 : ~data_misaligned_ex_i & wb_ready_i;
regfile_we_wb_power_o = (COREV_PULP == 0) ? 1'b1 : ~data_misaligned_ex_i & wb_ready_i;
if (apu_valid & (!apu_singlecycle & !apu_multicycle)) begin
wb_contention_lsu = 1'b1;
end
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