Update documentation of instruction extensions for CV32E40P version 2. #760
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Automatic PR dev->master
Automatic PR dev->master
Automatic PR dev->master
Automatic PR dev->master
Automatic PR dev->master
Automatic PR dev->master
Automatic PR dev->master
| * ALU extensions, see :ref:`corev_alu`. | ||
| * Multiply-Accumulate extensions, see :ref:`corev_multiply_accumulate`. | ||
| * Single Instruction Multiple Data (aka SIMD) extensions, see :ref:`corev_simd`. | ||
| * Post-Incrementing load and stores, see :ref:`corev_load_store`, invoked in the tool chain with ``-march=xcvmem``. |
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Do we need to be more precise like -march=rv32i*_xcvmem
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That's a good suggestion. I'll make this change.
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| Additionally the event load instruction (**cv.elw**) is supported by setting ``PULP_CLUSTER`` == 1, see :ref:`corev_event_load`. This is a separate ISA extension, invoked in the tool chain with ``-march=xcvelw``. | ||
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| To use such instructions, you need to compile your SW with the CORE-V GCC or Clang/LLVM compiler. |
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Maybe we should specify starting from which version those instructions are supported by the toolchain, GCC and LLVM.
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A good suggestion. I'll make this change.
| @@ -1066,9 +1071,6 @@ performed. | |||
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| The custom SIMD extensions are only supported if ``PULP_XPULP`` == 1. | |||
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| **SIMD is not supported by the compiler of the tool chain** as it is not implementing auto-vectorization up to now. | |||
| But those instructions can be used either with builtins or even in assembly. | |||
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I think we should keep this comment because it is still true.
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I will modify it. SIMD will be supported, but we won't have autovectization.
These changes particularly relate to how tool chain support is invoked using -march. We take the opportunity to remove caveats about ISA extensions not supported in the tool chain, since all are now supported in both GCC and Clang/LLVM. * docs/source/instruction_set_extensions.rst: Add -march tool chain invocations for each ISA extension and remove all caveats about compiler support. Signed-off-by: Jeremy Bennett <[email protected]>
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All comments by @pascalgouedo accepted and updated version force pushed. |
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* Correcting RFVI trace * Some clarifications about immediate in scalar replication on SIMD instructions. Signed-off-by: Pascal Gouedo <[email protected]> * Headers alignement. Signed-off-by: Pascal Gouedo <[email protected]> * Changed uvm_error in uvm_info in old tracer to avoid errors and header alignement. Signed-off-by: Pascal Gouedo <[email protected]> * Moved typedef definitions in rvfi_pkg and header alignement. Signed-off-by: Pascal Gouedo <[email protected]> * launched verible Signed-off-by: Pascal Gouedo <[email protected]> * Update documentation of instruction extensions for CV32E40P version 2. (#760) * Restored correct syntax * Update documentation of instruction extensions for CV32E40P version 2. These changes particularly relate to how tool chain support is invoked using -march. We take the opportunity to remove caveats about ISA extensions not supported in the tool chain, since all are now supported in both GCC and Clang/LLVM. * docs/source/instruction_set_extensions.rst: Add -march tool chain invocations for each ISA extension and remove all caveats about compiler support. Signed-off-by: Jeremy Bennett <[email protected]> --------- Signed-off-by: Jeremy Bennett <[email protected]> Co-authored-by: Davide Schiavone <[email protected]> Co-authored-by: pascalgouedo <[email protected]> --------- Signed-off-by: Pascal Gouedo <[email protected]> Signed-off-by: Jeremy Bennett <[email protected]> Co-authored-by: Yoann Pruvost <[email protected]> Co-authored-by: pascalgouedo <[email protected]> Co-authored-by: Jeremy Bennett <[email protected]> Co-authored-by: Davide Schiavone <[email protected]>
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* Restored correct syntax * Automatic PR dev->master (#766) * Correcting RFVI trace * Some clarifications about immediate in scalar replication on SIMD instructions. Signed-off-by: Pascal Gouedo <[email protected]> * Headers alignement. Signed-off-by: Pascal Gouedo <[email protected]> * Changed uvm_error in uvm_info in old tracer to avoid errors and header alignement. Signed-off-by: Pascal Gouedo <[email protected]> * Moved typedef definitions in rvfi_pkg and header alignement. Signed-off-by: Pascal Gouedo <[email protected]> * launched verible Signed-off-by: Pascal Gouedo <[email protected]> * Update documentation of instruction extensions for CV32E40P version 2. (#760) * Restored correct syntax * Update documentation of instruction extensions for CV32E40P version 2. These changes particularly relate to how tool chain support is invoked using -march. We take the opportunity to remove caveats about ISA extensions not supported in the tool chain, since all are now supported in both GCC and Clang/LLVM. * docs/source/instruction_set_extensions.rst: Add -march tool chain invocations for each ISA extension and remove all caveats about compiler support. Signed-off-by: Jeremy Bennett <[email protected]> --------- Signed-off-by: Jeremy Bennett <[email protected]> Co-authored-by: Davide Schiavone <[email protected]> Co-authored-by: pascalgouedo <[email protected]> --------- Signed-off-by: Pascal Gouedo <[email protected]> Signed-off-by: Jeremy Bennett <[email protected]> Co-authored-by: Yoann Pruvost <[email protected]> Co-authored-by: pascalgouedo <[email protected]> Co-authored-by: Jeremy Bennett <[email protected]> Co-authored-by: Davide Schiavone <[email protected]> * new block diagram (#14) --------- Signed-off-by: Pascal Gouedo <[email protected]> Signed-off-by: Jeremy Bennett <[email protected]> Co-authored-by: pascalgouedo <[email protected]> Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> Co-authored-by: Yoann Pruvost <[email protected]> Co-authored-by: Jeremy Bennett <[email protected]>
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Signed-off-by: Jeremy Bennett [email protected]