Automatic PR dev->master

bhv/cv32e40p_rvfi_trace.sv

@@ -0,0 +1,116 @@
+
+module cv32e40p_rvfi_trace
+  import cv32e40p_pkg::*;
+(
+    input logic clk_i,
+    input logic rst_ni,
+
+    input logic [31:0] hart_id_i,
+
+    input logic [31:0] imm_s3_type,
+
+    input logic        rvfi_valid,
+    input logic [31:0] rvfi_insn,
+    input logic [31:0] rvfi_pc_rdata,
+
+    input logic [ 4:0] rvfi_rd_addr,
+    input logic [31:0] rvfi_rd_wdata,
+    input logic [ 4:0] rvfi_rs1_addr,
+    input logic [ 4:0] rvfi_rs2_addr,
+    input logic [31:0] rvfi_rs1_rdata,
+    input logic [31:0] rvfi_rs2_rdata
+);
+
+  import cv32e40p_tracer_pkg::*;
+
+  logic rst_n;
+  assign rst_n = rst_ni;
+
+  integer f;  //file pointer
+  string  fn;
+  integer cycles;
+  string  info_tag;
+
+  logic [5:0] rd, rs1, rs2, rs3, rs4;
+  //TODO get from rvfi
+  logic [31:0] rs1_value;
+  logic [31:0] rs2_value;
+  logic [31:0] rs3_value;
+
+  logic [31:0] rs2_value_vec;
+
+  logic [31:0] imm_u_type;
+  logic [31:0] imm_uj_type;
+  logic [31:0] imm_i_type;
+  logic [11:0] imm_iz_type;
+  logic [31:0] imm_z_type;
+  logic [31:0] imm_s_type;
+  logic [31:0] imm_sb_type;
+  logic [31:0] imm_s2_type;
+  logic [31:0] imm_vs_type;
+  logic [31:0] imm_vu_type;
+  logic [31:0] imm_shuffle_type;
+  logic [ 4:0] imm_clip_type;
+
+  assign rd = rvfi_rd_addr;
+  assign rs1 = rvfi_rs1_addr;
+  assign rs2 = rvfi_rs2_addr;
+  assign rs3 = '0;
+  assign rs4 = '0;
+
+  assign rs1_value = rvfi_rs1_rdata;
+  assign rs2_value = rvfi_rs2_rdata;
+  assign rs3_value = rvfi_rd_wdata;
+
+  assign imm_u_typ = '0;
+  assign imm_uj_typ = '0;
+  assign imm_i_typ = '0;
+  assign imm_iz_typ = '0;
+  assign imm_z_typ = '0;
+  assign imm_s_typ = '0;
+  assign imm_sb_typ = '0;
+  assign imm_s2_typ = '0;
+  assign imm_vs_typ = '0;
+  assign imm_vu_typ = '0;
+  assign imm_shuffle_typ = '0;
+  assign imm_clip_typ = '0;
+
+  localparam FPU = 0;
+  localparam PULP_ZFINX = 0;
+  `include "cv32e40p_instr_trace.svh"
+instr_trace_t trace_retire;
+
+  function instr_trace_t trace_new_instr();
+    instr_trace_t trace;
+
+    trace = new();
+    trace.init(.cycles(cycles), .pc(rvfi_pc_rdata), .compressed(0), .instr(rvfi_insn));
+    return trace;
+  endfunction : trace_new_instr
+
+  // cycle counter
+  always_ff @(posedge clk_i, negedge rst_ni) begin
+    if (rst_ni == 1'b0) cycles <= 0;
+    else cycles <= cycles + 1;
+  end
+
+  always @(posedge clk_i) begin
+    if (rvfi_valid) begin
+      trace_retire = trace_new_instr();
+
+      trace_retire.printInstrTrace();
+    end
+  end
+
+  initial begin
+    wait(rst_n == 1'b1);
+    $sformat(fn, "trace_core.log");
+    $sformat(info_tag, "CORE_TRACER %2d", hart_id_i);
+    $display("[%s] Output filename is: %s", info_tag, fn);
+    f = $fopen(fn, "w");
+    $fwrite(f, "Time\tCycle\tPC\tInstr\tDecoded instruction\tRegister and memory contents\n");
+  end
+
+
+
+endmodule

bhv/cv32e40p_tb_wrapper.sv

@@ -25,7 +25,14 @@
 `include "cv32e40p_tracer.sv"
 `endif
 
-module cv32e40p_tb_wrapper #(
+`ifdef CV32E40P_RVFI
+`include "cv32e40p_rvfi.sv"
+`include "cv32e40p_rvfi_trace.sv"
+`endif
+
+module cv32e40p_tb_wrapper
+  import cv32e40p_pkg::*;
+#(
     parameter PULP_XPULP       = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw)
     parameter PULP_CLUSTER = 0,  // PULP Cluster interface (incl. p.elw)
     parameter FPU = 0,  // Floating Point Unit (interfaced via APU interface)
@@ -192,6 +199,121 @@ module cv32e40p_tb_wrapper #(
   );
 `endif
 
+`ifdef CV32E40P_RVFI
+  cv32e40p_rvfi rvfi_i (
+      .clk_i (cv32e40p_wrapper_i.core_i.clk_i),
+      .rst_ni(cv32e40p_wrapper_i.core_i.rst_ni),
+
+      .is_decoding_i    (cv32e40p_wrapper_i.core_i.id_stage_i.is_decoding_o),
+      .is_illegal_i     (cv32e40p_wrapper_i.core_i.id_stage_i.illegal_insn_dec),
+      .data_misaligned_i(cv32e40p_wrapper_i.core_i.data_misaligned),
+      .lsu_data_we_ex_i (cv32e40p_wrapper_i.core_i.data_we_ex),
+      //// IF probes ////
+      .instr_valid_if_i (cv32e40p_wrapper_i.core_i.if_stage_i.instr_valid),
+      .if_valid_i       (cv32e40p_wrapper_i.core_i.if_stage_i.if_valid),
+      .instr_if_i       (cv32e40p_wrapper_i.core_i.if_stage_i.instr_aligned),
+      //// ID probes ////
+      .pc_id_i          (cv32e40p_wrapper_i.core_i.id_stage_i.pc_id_i),
+      .id_valid_i       (cv32e40p_wrapper_i.core_i.id_stage_i.id_valid_o),
+
+      .rs1_addr_id_i     (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_addr_ra_id[4:0]), // FIXME: width mismatch
+      .rs2_addr_id_i     (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_addr_rb_id[4:0]), // FIXME: width mismatch
+      .operand_a_fw_id_i(cv32e40p_wrapper_i.core_i.id_stage_i.operand_a_fw_id),
+      .operand_b_fw_id_i(cv32e40p_wrapper_i.core_i.id_stage_i.operand_b_fw_id),
+      // .instr         (cv32e40p_wrapper_i.core_i.id_stage_i.instr     ),
+      .is_compressed_id_i(cv32e40p_wrapper_i.core_i.id_stage_i.is_compressed_i),
+
+      //// EX probes ////
+      .ex_valid_i  (cv32e40p_wrapper_i.core_i.ex_valid),
+      .ex_reg_addr (cv32e40p_wrapper_i.core_i.regfile_alu_waddr_fw[4:0]), // FIXME: width mismatch
+      .ex_reg_we   (cv32e40p_wrapper_i.core_i.regfile_alu_we_fw),
+      .ex_reg_wdata(cv32e40p_wrapper_i.core_i.regfile_alu_wdata_fw),
+
+      // .rf_we_alu_i    (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_alu_we_fw_i),
+      // .rf_addr_alu_i  (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_alu_waddr_fw_i),
+      // .rf_wdata_alu_i (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_alu_wdata_fw_i),
+
+      //// WB probes ////
+      .wb_valid_i(cv32e40p_wrapper_i.core_i.wb_valid),
+
+
+      // Register writes
+      .rf_we_wb_i(cv32e40p_wrapper_i.core_i.id_stage_i.regfile_we_wb_i),
+      .rf_addr_wb_i (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_waddr_wb_i[4:0]), // FIXME: width mismatch
+      .rf_wdata_wb_i(cv32e40p_wrapper_i.core_i.id_stage_i.regfile_wdata_wb_i),
+
+
+      // Controller FSM probes
+      .ctrl_fsm_cs_i(cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs),
+
+      //CSR
+      .csr_addr_i     (cv32e40p_wrapper_i.core_i.cs_registers_i.csr_addr_i),
+      .csr_we_i       (cv32e40p_wrapper_i.core_i.cs_registers_i.csr_we_int),
+      .csr_wdata_int_i(cv32e40p_wrapper_i.core_i.cs_registers_i.csr_wdata_int),
+
+      .csr_mstatus_n_i(cv32e40p_wrapper_i.core_i.cs_registers_i.mstatus_n),
+      .csr_mstatus_q_i(cv32e40p_wrapper_i.core_i.cs_registers_i.mstatus_q),
+
+      .csr_misa_n_i(cv32e40p_wrapper_i.core_i.cs_registers_i.MISA_VALUE),  // WARL
+      .csr_misa_q_i(cv32e40p_wrapper_i.core_i.cs_registers_i.MISA_VALUE),
+
+      .csr_tdata1_n_i           (cv32e40p_wrapper_i.core_i.cs_registers_i.tmatch_control_rdata),//csr_wdata_int                                   ),
+      .csr_tdata1_q_i           (cv32e40p_wrapper_i.core_i.cs_registers_i.tmatch_control_rdata),//gen_trigger_regs.tmatch_control_exec_q          ),
+      .csr_tdata1_we_i(cv32e40p_wrapper_i.core_i.cs_registers_i.gen_trigger_regs.tmatch_control_we),
+
+      .csr_tinfo_n_i({16'h0, cv32e40p_wrapper_i.core_i.cs_registers_i.tinfo_types}),
+      .csr_tinfo_q_i({16'h0, cv32e40p_wrapper_i.core_i.cs_registers_i.tinfo_types}),
+
+      .csr_mie_n_i       (cv32e40p_wrapper_i.core_i.cs_registers_i.mie_n),
+      .csr_mie_q_i       (cv32e40p_wrapper_i.core_i.cs_registers_i.mie_q),
+      .csr_mie_we_i      (cv32e40p_wrapper_i.core_i.cs_registers_i.csr_mie_we),
+      .csr_mtvec_n_i     (cv32e40p_wrapper_i.core_i.cs_registers_i.mtvec_n),
+      .csr_mtvec_q_i     (cv32e40p_wrapper_i.core_i.cs_registers_i.mtvec_q),
+      .csr_mtvec_mode_n_i(cv32e40p_wrapper_i.core_i.cs_registers_i.mtvec_mode_n),
+      .csr_mtvec_mode_q_i(cv32e40p_wrapper_i.core_i.cs_registers_i.mtvec_mode_q),
+
+      .csr_mcountinhibit_q_i (cv32e40p_wrapper_i.core_i.cs_registers_i.mcountinhibit_q),
+      .csr_mcountinhibit_n_i (cv32e40p_wrapper_i.core_i.cs_registers_i.mcountinhibit_n),
+      .csr_mcountinhibit_we_i(cv32e40p_wrapper_i.core_i.cs_registers_i.mcountinhibit_we),
+
+      .csr_mscratch_q_i(cv32e40p_wrapper_i.core_i.cs_registers_i.mscratch_q),
+      .csr_mscratch_n_i(cv32e40p_wrapper_i.core_i.cs_registers_i.mscratch_n),
+      .csr_mepc_q_i    (cv32e40p_wrapper_i.core_i.cs_registers_i.mepc_q),
+      .csr_mepc_n_i    (cv32e40p_wrapper_i.core_i.cs_registers_i.mepc_n),
+      .csr_mcause_q_i  (cv32e40p_wrapper_i.core_i.cs_registers_i.mcause_q),
+      .csr_mcause_n_i  (cv32e40p_wrapper_i.core_i.cs_registers_i.mcause_n),
+
+      .csr_dcsr_q_i(cv32e40p_wrapper_i.core_i.cs_registers_i.dcsr_q),
+      .csr_dcsr_n_i(cv32e40p_wrapper_i.core_i.cs_registers_i.dcsr_n),
+
+      .csr_mhpmcounter_q_i(cv32e40p_wrapper_i.core_i.cs_registers_i.mhpmcounter_q),
+      .csr_mhpmcounter_write_lower_i (cv32e40p_wrapper_i.core_i.cs_registers_i.mhpmcounter_write_lower                     ),
+      .csr_mhpmcounter_write_upper_i (cv32e40p_wrapper_i.core_i.cs_registers_i.mhpmcounter_write_upper                     ),
+
+      .csr_mvendorid_i({
+        MVENDORID_BANK, MVENDORID_OFFSET
+      }),  //TODO: get this from the design instead of the pkg
+      .csr_marchid_i(MARCHID)  //TODO: get this from the design instead of the pkg
+  );
+
+  bind cv32e40p_rvfi: rvfi_i cv32e40p_rvfi_trace cv32e40p_tracer_i (
+      .clk_i(clk_i),
+      .rst_ni(rst_ni),
+      .hart_id_i(cv32e40p_wrapper_i.core_i.hart_id_i),
+
+      .imm_s3_type(cv32e40p_wrapper_i.core_i.id_stage_i.imm_s3_type),
+
+      .rvfi_valid(rvfi_valid),
+      .rvfi_insn(rvfi_insn),
+      .rvfi_pc_rdata(rvfi_pc_rdata),
+      .rvfi_rd_addr(rvfi_rd_addr),
+      .rvfi_rd_wdata(rvfi_rd_wdata),
+      .rvfi_rs1_addr(rvfi_rs1_addr),
+      .rvfi_rs2_addr(rvfi_rs2_addr),
+      .rvfi_rs1_rdata(rvfi_rs1_rdata),
+      .rvfi_rs2_rdata(rvfi_rs2_rdata)
+  );
+`endif
   // Instantiate the Core and the optinal FPU
   cv32e40p_wrapper #(
       .PULP_XPULP      (PULP_XPULP),

bhv/include/cv32e40p_rvfi_pkg.sv

@@ -0,0 +1,124 @@
+// Copyright (c) 2020 OpenHW Group
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+
+// Includes to print info about the RVFI output
+// Contributors: Davide Schiavone <[email protected]>
+//               Halfdan Bechmann <[email protected]>
+
+package cv32e40p_rvfi_pkg;
+  import cv32e40p_pkg::*;
+
+  // RVFI only supports MHPMCOUNTER_WIDTH == 64
+  parameter MHPMCOUNTER_WORDS = MHPMCOUNTER_WIDTH / 32;
+
+  parameter STAGE_IF = 0;
+  parameter STAGE_ID = 1;
+  parameter STAGE_EX = 2;
+  parameter STAGE_WB = 3;
+
+  typedef enum logic [1:0] {  // Memory error types
+    MEM_ERR_PMP      = 2'h2,
+    MEM_ERR_ATOMIC   = 2'h1,
+    MEM_ERR_IO_ALIGN = 2'h0
+  } mem_err_t;
+
+  typedef struct packed {  // Autonomously updated CSRs
+    logic [31:0] mcycle;
+    logic [31:0] mcycleh;
+    logic [31:0] cycle;
+    logic [31:0] cycleh;
+    logic [31:0] mip;
+    logic nmip;
+  } rvfi_auto_csr_map_t;
+
+  typedef struct packed {
+    logic [31:0] jvt;
+    logic [31:0] mstatus;
+    logic [31:0] misa;
+    logic [31:0] mie;
+    logic [31:0] mtvec;
+    logic [31:0] mstatush;
+    logic [31:0] mtvt;
+    logic [31:0] mcountinhibit;
+    logic [31:0][31:0] mhpmevent;
+    logic [31:0] mscratch;
+    logic [31:0] mepc;
+    logic [31:0] mcause;
+    logic [31:0] mtval;
+    logic [31:0] mip;
+    logic [31:0] mnxti;
+    logic [31:0] mintstatus;
+    logic [31:0] mintthresh;
+    logic [31:0] mscratchcsw;
+    logic [31:0] mscratchcswl;
+    logic [31:0] mclicbase;
+    logic [31:0] tselect;
+    logic [3:0][31:0] tdata;
+    logic [31:0] tinfo;
+    logic [31:0] mcontext;
+    logic [31:0] scontext;
+    logic [31:0] dcsr;
+    logic [31:0] dpc;
+    logic [1:0][31:0] dscratch;
+    logic [31:0] mcycle;
+    logic [31:0] minstret;
+    logic [31:0][31:0] mhpmcounter;
+    logic [31:0] mcycleh;
+    logic [31:0] minstreth;
+    logic [31:0][31:0] mhpmcounterh;
+    logic [31:0] cycle;
+    logic [31:0] instret;
+    logic [31:0][31:0] hpmcounter;
+    logic [31:0] cycleh;
+    logic [31:0] instreth;
+    logic [31:0][31:0] hpmcounterh;
+    logic [31:0] mvendorid;
+    logic [31:0] marchid;
+    logic [31:0] mimpid;
+    logic [31:0] mhartid;
+    logic [31:0] mcounteren;
+    logic [3:0][31:0] pmpcfg;
+    logic [15:0][31:0] pmpaddr;
+    logic [31:0] mseccfg;
+    logic [31:0] mseccfgh;
+    logic [31:0] mconfigptr;
+
+  } rvfi_csr_map_t;
+
+  typedef struct packed {
+    logic [10:0] cause;
+    logic debug;
+    logic interrupt;
+    logic wu;
+  } rvfi_wu_t;
+
+  typedef struct packed {
+    logic [10:0] cause;
+    logic interrupt;
+    logic exception;
+    logic intr;
+  } rvfi_intr_t;
+
+  typedef struct packed {
+    logic [1:0] cause_type;
+    logic [2:0] debug_cause;
+    logic [5:0] exception_cause;
+    logic debug;
+    logic exception;
+    logic trap;
+  } rvfi_trap_t;
+
+endpackage  // cv32e40p_rvfi_pkg

docs/source/corev_hw_loop.rst

@@ -92,7 +92,7 @@ a matrix addition.
 
    asm volatile (
        ".option norvc;"
-       "add %[j],x0, x0;"
+       "add %[i],x0, x0;"
        "add %[j],x0, x0;"
        "cv.count  x1, %[N];"
        "cv.endi   x1, endO;"
@@ -111,7 +111,7 @@ a matrix addition.
 
 
 At the beginning of the HWLoop, the registers %[i] and %[j] are 0.
-The innermost loop, from start0 to end0, adds to %[i] three times 1 and
+The innermost loop, from startZ to endZ, adds to %[i] three times 1 and
 it is executed 10x10 times. Whereas the outermost loop, from startO to endO,
 executes 10 times the innermost loop and adds two times 2 to the register %[j].
 At the end of the loop, the register %[i] contains 300 and the register %[j] contains 40.