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FPU integration in cv32e40p_wrapper #707
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davideschiavone
merged 4 commits into
openhwgroup:dev
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pascalgouedo:dev_pgo_fpu_integration
Jun 20, 2022
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,87 @@ | ||
| /////////////////////////////////////////////////////////////////////////////// | ||
| // | ||
| // Copyright 2020 OpenHW Group | ||
| // | ||
| // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); | ||
| // you may not use this file except in compliance with the License. | ||
| // You may obtain a copy of the License at | ||
| // | ||
| // https://solderpad.org/licenses/ | ||
| // | ||
| // Unless required by applicable law or agreed to in writing, software | ||
| // distributed under the License is distributed on an "AS IS" BASIS, | ||
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| // See the License for the specific language governing permissions and | ||
| // limitations under the License. | ||
| // | ||
| /////////////////////////////////////////////////////////////////////////////// | ||
| // | ||
| // Manifest for the CV32E40P RTL model. | ||
| // - Intended to be used by both synthesis and simulation. | ||
| // - Relevent synthesis and simulation scripts/Makefiles must set the shell | ||
| // ENV variable DESIGN_RTL_DIR as required. | ||
| // | ||
| /////////////////////////////////////////////////////////////////////////////// | ||
|
|
||
| +incdir+${DESIGN_RTL_DIR}/include | ||
| +incdir+${DESIGN_RTL_DIR}/../bhv | ||
| +incdir+${DESIGN_RTL_DIR}/../bhv/include | ||
| +incdir+${DESIGN_RTL_DIR}/../sva | ||
| +incdir+${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/include | ||
|
|
||
| ${DESIGN_RTL_DIR}/include/cv32e40p_apu_core_pkg.sv | ||
| ${DESIGN_RTL_DIR}/include/cv32e40p_fpu_pkg.sv | ||
| ${DESIGN_RTL_DIR}/include/cv32e40p_pkg.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_if_stage.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_cs_registers.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_register_file_ff.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_load_store_unit.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_id_stage.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_aligner.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_decoder.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_compressed_decoder.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_fifo.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_prefetch_buffer.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_hwloop_regs.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_mult.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_int_controller.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_ex_stage.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_alu_div.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_alu.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_ff_one.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_popcnt.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_apu_disp.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_controller.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_obi_interface.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_prefetch_controller.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_sleep_unit.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_core.sv | ||
|
|
||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/src/cf_math_pkg.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/src/rr_arb_tree.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_common_cells/src/lzc.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/control_mvp.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_pkg.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_classifier.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_rounding.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_cast_multi.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_fma_multi.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_noncomp.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_opgroup_fmt_slice.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_opgroup_multifmt_slice.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_opgroup_block.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_divsqrt_multi.sv | ||
| ${DESIGN_RTL_DIR}/vendor/pulp_platform_fpnew/src/fpnew_top.sv | ||
| ${DESIGN_RTL_DIR}/cv32e40p_fp_wrapper.sv | ||
|
|
||
| ${DESIGN_RTL_DIR}/cv32e40p_wrapper.sv | ||
|
|
||
| ${DESIGN_RTL_DIR}/../bhv/cv32e40p_sim_clock_gate.sv | ||
| ${DESIGN_RTL_DIR}/../bhv/include/cv32e40p_tracer_pkg.sv | ||
| ${DESIGN_RTL_DIR}/../bhv/cv32e40p_tb_wrapper.sv |
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why did we delete the tracer_pkg?
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I didn't remove it, just moved it at the bottom before tb_wrapper to have clear separation between CV32 IP and behavioural/test-bench stuff.