Table rendering

Signed-off-by: Pascal Gouedo <[email protected]>
openhwgroup · Jun 3, 2024 · cf658a0 · cf658a0
1 parent 1dbddd8
commit cf658a0
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/scripts/riscv_isa_formal/README.md b/scripts/riscv_isa_formal/README.md
@@ -4,8 +4,8 @@ RISC-V ISA Formal Verification methodology has been used with Siemens EDA Onespi
 
 ## Configurations
 
-  | **Top Parameters** | **XP** | **XPF0** | **XPF1** | **XPF2** | **XPZF0** | **XPZF1** | **XPZF2** |
-  |--------------------|-----------------------------------------------------------------------------|
+  | Top Parameters     | XP     | XPF0     | XPF1     | XPF2     | XPZF0     | XPZF1     | XPZF2     |
+  | :----------------- | :----: |:-------: | :------: | :------: | :-------: | :-------: | :-------: |
   | COREV_PULP         | 1      | 1        | 1        | 1        | 1         | 1         | 1         |
   | COREV_CLUSTER      | 0      | 0        | 0        | 0        | 0         | 0         | 0         |
   | FPU                | 0      | 1        | 1        | 1        | 1         | 1         | 1         |