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Merge pull request #974 from pascalgouedo/dev_dd_pgo_lec
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Added new apu_busy_o at cv32e40p_core level for v1 lec and fpu latency parameters for v2 lec.
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davideschiavone authored Apr 4, 2024
2 parents af03d59 + aa1bac6 commit 3bfea13
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Showing 4 changed files with 23 additions and 8 deletions.
3 changes: 2 additions & 1 deletion .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -19,9 +19,10 @@ TAGS
/Bender.lock
/Bender.local
golden_reference_design
ref_design
golden.src
revised.src
cadence_conformal
synopsys_formality
questa_autocheck
slec/reports
reports
6 changes: 4 additions & 2 deletions scripts/slec/cadence/lec.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -20,11 +20,12 @@ set version $::env(version)
set pulp_cfg $::env(pulp_cfg)
set fpu_cfg $::env(fpu_cfg)
set zfinx_cfg $::env(zfinx_cfg)
set latency_cfg $::env(latency_cfg)

if {"$version" == "v1"} {
set golden_parameter_list "-parameter PULP_XPULP 0 -parameter FPU 0 -parameter PULP_ZFINX 0"
} else {
set golden_parameter_list "-parameter COREV_PULP $pulp_cfg -parameter FPU $fpu_cfg -parameter ZFINX $zfinx_cfg"
set golden_parameter_list "-parameter COREV_PULP $pulp_cfg -parameter FPU $fpu_cfg -parameter ZFINX $zfinx_cfg -parameter FPU_ADDMUL_LAT $latency_cfg -parameter FPU_OTHERS_LAT $latency_cfg"
}

read_design -SV09 -replace -noelaborate -golden -File ./golden.src
Expand All @@ -33,7 +34,7 @@ elaborate_design -golden -root $top_module $golden_parameter_list

read_design -SV09 -replace -noelaborate -revised -File ./revised.src

elaborate_design -revised -root $top_module -parameter COREV_PULP $pulp_cfg -parameter FPU $fpu_cfg -parameter ZFINX $zfinx_cfg
elaborate_design -revised -root $top_module -parameter COREV_PULP $pulp_cfg -parameter FPU $fpu_cfg -parameter ZFINX $zfinx_cfg -parameter FPU_ADDMUL_LAT $latency_cfg -parameter FPU_OTHERS_LAT $latency_cfg

report_design_data

Expand All @@ -42,6 +43,7 @@ if {"$top_module" == "cv32e40p_core"} {
add_ignored_outputs apu_operands_o* -Both
add_ignored_outputs apu_op_o* -Both
add_ignored_outputs apu_flags_o* -Both
add_ignored_outputs apu_busy_o -Revised
}

write_hier_compare_dofile hier_compare_r2r.do -constraint -replace
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14 changes: 12 additions & 2 deletions scripts/slec/run.sh
Original file line number Diff line number Diff line change
Expand Up @@ -17,9 +17,10 @@
# limitations under the License.

usage() { # Function: Print a help message.
echo "Usage: $0 -t {cadence,synopsys,siemens} -p {sec,lec} [-v {v1,v2}] [-x {0,1}] [-f {0,1}] [-z {0,1}]]" 1>&2
echo "Usage: $0 -t {cadence,synopsys,siemens} -p {sec,lec} [-v {v1,v2}] [-x {0,1}] [-f {0,1}] [-z {0,1}] [-l {0,1,2}]]" 1>&2
echo "For v2 : if f or z is 1 then p must be 1" 1>&2
echo " if z is 1 then f must be 1" 1>&2
echo " l only 1 or 2 if f is 1" 1>&2
}

exit_abnormal() { # Function: Exit with error.
Expand All @@ -40,8 +41,9 @@ VERSION=v1
PULP_CFG=0
FPU_CFG=0
ZFINX_CFG=0
LATENCY_CFG=0

while getopts "t:p:v:x:f:z:" flag
while getopts "t:p:v:x:f:z:l:" flag
do
case "${flag}" in
t)
Expand All @@ -62,6 +64,9 @@ do
z)
ZFINX_CFG=${OPTARG}
;;
l)
LATENCY_CFG=${OPTARG}
;;
:)
exit_abnormal
;;
Expand Down Expand Up @@ -104,6 +109,10 @@ if [[ (("${PULP_CFG}" == 0 && ("${FPU_CFG}" == 1 || "${ZFINX_CFG}" == 1)) || ("$
exit_abnormal
fi

if [[ ("${FPU_CFG}" == 0 && ("${LATENCY_CFG}" == 1 || "${LATENCY_CFG}" == 2)) ]]; then
exit_abnormal
fi

if [[ "${VERSION}" == "v1" ]]; then
REF_BRANCH=cv32e40p_v1.0.0
TOP_MODULE=cv32e40p_core
Expand All @@ -117,6 +126,7 @@ export version=${VERSION}
export pulp_cfg=${PULP_CFG}
export fpu_cfg=${FPU_CFG}
export zfinx_cfg=${ZFINX_CFG}
export latency_cfg=${LATENCY_CFG}

if [ -z "${REF_REPO}" ]; then
print_log "Empty REF_REPO env variable"
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8 changes: 5 additions & 3 deletions scripts/slec/synopsys/lec.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -21,22 +21,23 @@ set version $::env(version)
set pulp_cfg $::env(pulp_cfg)
set fpu_cfg $::env(fpu_cfg)
set zfinx_cfg $::env(zfinx_cfg)
set latency_cfg $::env(latency_cfg)

set core_impl_name cv32e40p_core_COREV_PULP${pulp_cfg}_FPU${fpu_cfg}_ZFINX${zfinx_cfg}
set core_impl_name cv32e40p_core_COREV_PULP${pulp_cfg}_FPU${fpu_cfg}_FPU_ADDMUL_LAT${latency_cfg}_FPU_OTHERS_LAT${latency_cfg}_ZFINX${zfinx_cfg}

if {"$version" == "v1"} {
set golden_parameter_list "PULP_XPULP = 0, FPU = 0, PULP_ZFINX = 0"
set core_ref_name cv32e40p_core_PULP_XPULP0_FPU0_PULP_ZFINX0
} else {
set golden_parameter_list "COREV_PULP = $pulp_cfg, FPU = $fpu_cfg, ZFINX = $zfinx_cfg"
set golden_parameter_list "COREV_PULP = $pulp_cfg, FPU = $fpu_cfg, ZFINX = $zfinx_cfg, FPU_ADDMUL_LAT = $latency_cfg, FPU_OTHERS_LAT = $latency_cfg"
set core_ref_name $core_impl_name
}

read_sverilog -container r -libname WORK -12 -f golden.src
set_top r:/WORK/$top_module -parameter $golden_parameter_list

read_sverilog -container i -libname WORK -12 -f revised.src
set_top i:/WORK/$top_module -parameter "COREV_PULP = $pulp_cfg, FPU = $fpu_cfg, ZFINX = $zfinx_cfg"
set_top i:/WORK/$top_module -parameter "COREV_PULP = $pulp_cfg, FPU = $fpu_cfg, ZFINX = $zfinx_cfg, FPU_ADDMUL_LAT = $latency_cfg, FPU_OTHERS_LAT = $latency_cfg"

match > $summary_log.match.rpt

Expand All @@ -49,6 +50,7 @@ if {"$top_module" == "cv32e40p_core"} {
set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_operands_o*
set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_op_o*
set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_flags_o*
set_dont_verify_point -type port i:/WORK/$core_impl_name/apu_busy_o
}

verify > $summary_log
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