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modified run_phase -> main_phase #2458

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modified run_phase -> main_phase #2458

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cafcd2a
modified run_phase -> main_phase
subbu009 May 31, 2024
61d8563
Removed waiting for posedge reset_n
subbu009 Jun 3, 2024
e798277
Merge branch 'cv32e40p/dev' of https://github.com/subbu009/core-v-ver…
subbu009 Jun 3, 2024
b3ed478
Added wait on reset_n
subbu009 Jun 5, 2024
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6 changes: 3 additions & 3 deletions cv32e40p/env/uvme/uvme_cv32e40p_env.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -88,7 +88,7 @@ class uvme_cv32e40p_env_c extends uvm_env;
/**
* Creates and starts the instruction and virtual peripheral sequences in active mode.
*/
extern virtual task run_phase(uvm_phase phase);
extern virtual task main_phase(uvm_phase phase);

/**
* Get virtual interface handles from UVM Configuration Database.
Expand Down Expand Up @@ -225,7 +225,7 @@ endfunction: connect_phase
// 2. The calls to randomize() are on sequences that are only randomized
// once in this ENV.
//
task uvme_cv32e40p_env_c::run_phase(uvm_phase phase);
task uvme_cv32e40p_env_c::main_phase(uvm_phase phase);

uvma_obi_memory_fw_preload_seq_c fw_preload_seq;
uvma_obi_memory_slv_seq_c instr_slv_seq;
Expand Down Expand Up @@ -310,7 +310,7 @@ task uvme_cv32e40p_env_c::run_phase(uvm_phase phase);
join_none
end

endtask : run_phase
endtask : main_phase
//@DVT_LINTER_WAIVER_END "MT20220302_01"


Expand Down
8 changes: 4 additions & 4 deletions cv32e40p/tests/uvmt/base-tests/uvmt_cv32e40p_base_test.sv
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Expand Up @@ -110,7 +110,7 @@ class uvmt_cv32e40p_base_test_c extends uvm_test;
* 1. Triggers the start of clock generation via start_clk()
* 2. Starts the watchdog timeout via watchdog_timeout()
*/
extern virtual task run_phase(uvm_phase phase);
extern virtual task main_phase(uvm_phase phase);

/**
* Runs reset_vseq.
Expand Down Expand Up @@ -262,13 +262,13 @@ function void uvmt_cv32e40p_base_test_c::end_of_elaboration_phase(uvm_phase phas
endfunction : end_of_elaboration_phase


task uvmt_cv32e40p_base_test_c::run_phase(uvm_phase phase);
task uvmt_cv32e40p_base_test_c::main_phase(uvm_phase phase);

super.run_phase(phase);
super.main_phase(phase);

watchdog_timer();

endtask : run_phase
endtask : main_phase


task uvmt_cv32e40p_base_test_c::reset_phase(uvm_phase phase);
Expand Down
10 changes: 5 additions & 5 deletions cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_firmware_test.sv
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Expand Up @@ -76,7 +76,7 @@ class uvmt_cv32e40p_firmware_test_c extends uvmt_cv32e40p_base_test_c;
/**
* Enable program execution, wait for completion.
*/
extern virtual task run_phase(uvm_phase phase);
extern virtual task main_phase(uvm_phase phase);

/**
* Start random debug sequencer
Expand Down Expand Up @@ -122,10 +122,10 @@ task uvmt_cv32e40p_firmware_test_c::configure_phase(uvm_phase phase);
endtask : configure_phase


task uvmt_cv32e40p_firmware_test_c::run_phase(uvm_phase phase);
task uvmt_cv32e40p_firmware_test_c::main_phase(uvm_phase phase);

// start_clk() and watchdog_timer() are called in the base_test
super.run_phase(phase);
super.main_phase(phase);

if ($test$plusargs("gen_random_debug") || $test$plusargs("gen_reduced_rand_dbg_req")) begin
fork
Expand All @@ -151,7 +151,7 @@ task uvmt_cv32e40p_firmware_test_c::run_phase(uvm_phase phase);
end

phase.raise_objection(this);
@(posedge env_cntxt.clknrst_cntxt.vif.reset_n);
wait(env_cntxt.clknrst_cntxt.vif.reset_n === 1'b1);
repeat (33) @(posedge env_cntxt.clknrst_cntxt.vif.clk);
`uvm_info("TEST", "Started RUN", UVM_NONE)
// The firmware is expected to write exit status and pass/fail indication to the Virtual Peripheral
Expand All @@ -165,7 +165,7 @@ task uvmt_cv32e40p_firmware_test_c::run_phase(uvm_phase phase);
`uvm_info("TEST", $sformatf("Finished RUN: exit status is %0h", vp_status_vif.exit_value), UVM_NONE)
phase.drop_objection(this);

endtask : run_phase
endtask : main_phase

task uvmt_cv32e40p_firmware_test_c::reset_debug();
uvme_cv32e40p_random_debug_reset_c debug_vseq;
Expand Down
10 changes: 5 additions & 5 deletions cv32e40p/tests/uvmt/compliance-tests/uvmt_cv32e40p_riscof_firmware_test.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,7 @@ class uvmt_cv32e40p_riscof_firmware_test_c extends uvmt_cv32e40p_base_test_c;
/**
* Enable program execution, wait for completion.
*/
extern virtual task run_phase(uvm_phase phase);
extern virtual task main_phase(uvm_phase phase);

extern function void write_riscof_signature();

Expand Down Expand Up @@ -139,12 +139,12 @@ function void uvmt_cv32e40p_riscof_firmware_test_c::post_randomize();
endfunction : post_randomize


task uvmt_cv32e40p_riscof_firmware_test_c::run_phase(uvm_phase phase);
task uvmt_cv32e40p_riscof_firmware_test_c::main_phase(uvm_phase phase);

super.run_phase(phase);
super.main_phase(phase);

phase.raise_objection(this);
@(posedge env_cntxt.clknrst_cntxt.vif.reset_n);
wait(env_cntxt.clknrst_cntxt.vif.reset_n === 1'b1);
repeat (33) @(posedge env_cntxt.clknrst_cntxt.vif.clk);
`uvm_info("TEST", "Started RUN", UVM_NONE)

Expand All @@ -162,7 +162,7 @@ task uvmt_cv32e40p_riscof_firmware_test_c::run_phase(uvm_phase phase);

phase.drop_objection(this);

endtask : run_phase
endtask : main_phase

function void uvmt_cv32e40p_riscof_firmware_test_c::write_riscof_signature();
bit[31:0] mem_read;
Expand Down