CV32E40Pv2 Verification update Week 17 PR #2417
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Signed-off-by: Pascal Gouedo <[email protected]>
Added new illegal cases for SIMD instructions.
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Changed bsp compilation march option to avoid HWloop use
Signed-off-by: Pascal Gouedo <[email protected]>
Updated cv.shuffle.sci.h Imm6 values to comply with v1.8.0 RTL
Signed-off-by: Pascal Gouedo <[email protected]>
…ine). Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Correction for HWloop use in bsp (indirectly through puts)
Signed-off-by: Bee Nee Lim <[email protected]>
Add license header on new test .S file
I also included a rework of CSR vplan as it did not match verification environment state when v2 project started + I completed it with new v2 verification items. HWLOOP Vplan as been updated: some interrupt/debug requirement has been detailed. Every file has been pushed as a new v2 file, to make it clearer that these plans target v2 verification. Old v1 plans could be reverted to a previous state to avoid confusion and to prevent history loss between projects
v2 plans back-annotation
Signed-off-by: dd-baoshan <[email protected]>
Signed-off-by: dd-baoshan <[email protected]>
…s_WW17 Cv32e40p/bsm update tb files ww17
Setting all mhpm csr to volatile in Imperas_dv_wrap
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Thanks for this @dd-BeeNee. Appreciated you adding the license headers!
I have one question in cv32e40p/bsp/handlers.S.
MikeOpenHWGroup
approved these changes
Apr 29, 2024
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This Pull Request contains the work from this week (ww17).
The updates are:
(Note: v1 test plans revert to original v1 state are not started yet, will come in next PR)