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Merge pull request #2405 from XavierAubert/cv32e40p/dev_dd_w15a
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CV32E40Pv2 Verification update Week 15
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@MikeOpenHWGroup
MikeOpenHWGroup authored Apr 8, 2024
2 parents 3592fdb + f79204d commit 6d973dd
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Showing 28 changed files with 4,670 additions and 90 deletions.
12 changes: 9 additions & 3 deletions cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -119,15 +119,18 @@ package cv32e40p_instr_test_pkg;
function automatic void push_gpr_to_debugger_stack(cv32e40p_instr_gen_config cfg_corev,
ref string instr[$]);
string store_instr = (XLEN == 32) ? "sw" : "sd";
// Reserve space from kernel stack to save all 32 GPR except for x0
instr.push_back($sformatf("1: addi x%0d, x%0d, -%0d", cfg_corev.dp, cfg_corev.dp, 31 * (XLEN/8)));
// Push all GPRs to kernel stack
// Reserve space from debugger stack to save all 32 GPR except for x0 + MSCRATCH
instr.push_back($sformatf("1: addi x%0d, x%0d, -%0d", cfg_corev.dp, cfg_corev.dp, 32 * (XLEN/8)));
// Push all GPRs to debugger stack
for(int i = 1; i < 32; i++) begin
if (i == cfg_corev.dp) continue;
if (i == cfg_corev.sp) continue;
if (i == cfg_corev.tp) continue;
instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", store_instr, i, (i-1) * (XLEN/8), cfg_corev.dp));
end
// Read and Push MSCRATCH to debugger stack
instr.push_back($sformatf("csrrw x5, 0x340, x5 # MSCRATCH"));
instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", store_instr, 5, 31 * (XLEN/8), cfg_corev.dp));
endfunction : push_gpr_to_debugger_stack

// Push floating point registers to the debugger stack
Expand Down Expand Up @@ -217,6 +220,9 @@ package cv32e40p_instr_test_pkg;
if (i == cfg_corev.tp) continue;
instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, i, (i-1) * (XLEN/8), cfg_corev.dp));
end
// Pop and Write MSCRATCH from debugger stack
instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, 5, 31 * (XLEN/8), cfg_corev.dp));
instr.push_back($sformatf("csrrw x5, 0x340, x5 # MSCRATCH"));
// Restore debugger stack pointer
instr.push_back($sformatf("addi x%0d, x%0d, %0d", cfg_corev.dp, cfg_corev.dp, 31 * (XLEN/8)));
endfunction : pop_gpr_from_debugger_stack
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55 changes: 22 additions & 33 deletions cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -57,44 +57,48 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream;
`uvm_fatal(`gfn, $sformatf("Function implementation is not ready for replace==1"))
end

if(current_instr_cnt == 0) begin
if (current_instr_cnt == 0) begin
instr_list = new_instr;
return;
end
if(idx == -1) begin

if (idx == -1) begin

bit idx_search_done = 0;
int rand_cnt = 0;

do begin
idx = $urandom_range(0, current_instr_cnt-1);
end while (instr_list[idx].atomic);
while (!instr_list[idx].atomic && !idx_search_done) begin
do begin : STREAM_PLACEMENT
int idx_e = 0;

idx = $urandom_range(1, current_instr_cnt-1);
idx_e = (idx + new_instr_cnt-1);

if (idx_start.size() == 0) begin : SEARCH_IDX_FOR_NEW_INSTR
if (idx_start.size() == 0) begin
idx_min = idx;
idx_search_done = 1;
end // SEARCH_IDX_FOR_NEW_INSTR
else begin
end
else if (instr_list[idx].atomic)begin : CHECK_IDX_OVERLAP_WITH_ATOMIC
idx_search_done = 0;
end // DETECT_OVERLAP_IDX_WITH_ATOMIC
else begin : CHECK_IDX_OVERLAP_WITH_PREV_STREAM
foreach (idx_start[i]) begin
if (
(idx >= idx_start[i] && idx <= idx_end[i]) ||
(idx_e >= idx_start[i] && idx_e <= idx_end[i]) ||
(idx_start[i] >= idx && idx_start[i] <= idx_e) ||
(idx_end[i] >= idx && idx_end[i] <= idx_e)
) begin : DETECT_OVERLAP_IDX_FOR_NEW_INSTR
(idx_end[i] >= idx && idx_end[i] <= idx_e))
begin : OVERLAP_IDX_AGAINST_PREV_STREAMS
idx_search_done = 0;
break;
end // DETECT_OVERLAP_IDX_FOR_NEW_INSTR
else begin : NON_OVERLAP_IDX_FOR_NEW_INSTR
end // OVERLAP_IDX_AGAINST_PREV_STREAMS
else begin : NO_OVERLAP_IDX_AGAINST_PREV_STREAMS
if (i == (idx_start.size()-1)) begin
idx_search_done = 1;
break;
end
end // NON_OVERLAP_IDX_FOR_NEW_INSTR
end // NO_OVERLAP_IDX_AGAINST_PREV_STREAMS
end // foreach
end // SEARCH_IDX_FOR_NEW_INSTR
end // CHECK_IDX_OVERLAP_WITH_PREV_STREAM

if (idx_search_done) begin
int idx_placement[$];
Expand Down Expand Up @@ -123,7 +127,7 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream;
if (rand_cnt >= 200) begin
int idx_placement[$];
`uvm_info(`gfn, $sformatf("placement limit %0d reached. Place the stream at begining of instr_list", rand_cnt), UVM_NONE)
idx = 0;
idx = 1;
idx_e = (idx + new_instr_cnt-1);
idx_start.push_front(idx);
idx_end.push_front(idx_e);
Expand All @@ -135,23 +139,8 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream;
break;
end // rand_cnt

do begin
idx = $urandom_range(0, current_instr_cnt-1);
end while (instr_list[idx].atomic);

end // while

if (instr_list[idx].atomic) begin
foreach (instr_list[i]) begin
if (!instr_list[i].atomic) begin
idx = i;
break;
end
end
if (instr_list[idx].atomic) begin
`uvm_fatal(`gfn, $sformatf("Cannot inject the instruction"))
end
end // instr_list[idx].atomic
end // STREAM_PLACEMENT
while (!idx_search_done);

end else if((idx > current_instr_cnt) || (idx < 0)) begin
`uvm_error(`gfn, $sformatf("Cannot insert instr stream at idx %0d", idx))
Expand Down
10 changes: 9 additions & 1 deletion cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv
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Expand Up @@ -215,8 +215,16 @@ class cv32e40p_xpulp_single_hwloop_stream_directed extends cv32e40p_xpulp_hwloop
}

constraint num_hwloop_instr_c {
solve use_loop_endi_inst before num_hwloop_instr;
foreach (num_hwloop_instr[i]) {
num_hwloop_instr[i] dist { 3 := 1, 3074 := 5, 4092 := 1 };
// the max setting of Uimm[11:0] is 4092 however the the hwloop start label is not immediately following after cv.endi,
// there is randomize numberof instr inserted between cv.endi and hwloop start label we need to keep some buffer from
// max value so that the number instr can never be max 4092 (-5 buffer for instrs prior hwloop)
if (use_loop_endi_inst[i]) {
num_hwloop_instr[i] dist { 3 := 1, 3074 := 5, 4087 := 1 };
} else {
num_hwloop_instr[i] dist { 3 := 1, 3074 := 5, 4092 := 1 };
}
num_fill_instr_loop_ctrl_to_loop_start[i] inside {[0:7]};
}
num_fill_instr_in_loop1_till_loop0_setup == 0;
Expand Down
28 changes: 22 additions & 6 deletions cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,7 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream;
rand int unsigned num_fill_instr_in_loop1_till_loop0_setup;
rand bit setup_l0_before_l1_start;

riscv_reg_t compress_regs[8] = {S0, S1, A0, A1, A2, A3, A4, A5};
int unsigned num_instr_cv_start_to_loop_start_label[2];
cv32e40p_instr hwloop_setupi_instr[2];
cv32e40p_instr hwloop_setup_instr[2];
Expand Down Expand Up @@ -395,6 +396,8 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream;
//*************************************************************

if(gen_nested_loop) begin //NESTED HWLOOP
bit std_rand_done = 0;
int unsigned std_rand_cnt = 0;
gen_cv_count0_instr = $urandom();

//calculate num_rem_hwloop1_instr
Expand All @@ -418,12 +421,25 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream;

//Initialize GPRs used as RS1 in HWLOOP Instructions
hwloop_avail_regs = new[6]; //index fixed for this stream from 0:2 for start0,end0,count0=setup0; 3:5 for start1,end1,count1=setup1 respectively
std::randomize(hwloop_avail_regs) with { unique {hwloop_avail_regs};
foreach(hwloop_avail_regs[i]) {
!(hwloop_avail_regs[i] inside {ZERO, RA, SP, GP, TP});
!(hwloop_avail_regs[i] inside {cfg.reserved_regs});
}
};
std_rand_cnt = 0;
do begin
int unsigned is_compress_reg_cnt = 0;
if (std_rand_cnt == 100) begin
`uvm_fatal(this.get_type_name(), "std randomization count limit hit, please review")
end
std::randomize(hwloop_avail_regs) with { unique {hwloop_avail_regs};
foreach(hwloop_avail_regs[i]) {
!(hwloop_avail_regs[i] inside {ZERO, RA, SP, GP, TP});
!(hwloop_avail_regs[i] inside {cfg.reserved_regs});
}
};
foreach (compress_regs[i]) begin
if (compress_regs[i] inside {cfg.reserved_regs, hwloop_avail_regs}) is_compress_reg_cnt++;
end
if (is_compress_reg_cnt == $size(compress_regs)) std_rand_done = 0; else std_rand_done = 1;
if (!std_rand_done) std_rand_cnt++;
end
while (!std_rand_done);

reserved_rd = hwloop_avail_regs;

Expand Down
8 changes: 5 additions & 3 deletions cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -508,7 +508,8 @@ class uvme_rv32x_hwloop_covg # (
check_ebreakm_entry(i); \
end \
if (is_pc_equal_lpend(hwloop_stat_``TYPE``.hwloop_csr, i, 0, cv32e40p_rvvi_vif.pc_rdata) && hwloop_stat_``TYPE``.track_lp_cnt[i] != 0) begin \
if (pending_irq) lpend_has_pending_irq_``TYPE``[i] = 1; \
// if (pending_irq) lpend_has_pending_irq_``TYPE``[i] = 1; \
if (pending_irq && cv32e40p_rvvi_vif.trap) lpend_has_pending_irq_``TYPE``[i] = 1; \
hwloop_stat_``TYPE``.track_lp_cnt[i]--; \
done_insn_list_capture_``TYPE``[i] = 1; \
assert(hwloop_stat_``TYPE``.track_lp_cnt[i] >= 0); \
Expand Down Expand Up @@ -543,7 +544,8 @@ class uvme_rv32x_hwloop_covg # (
check_ebreakm_entry(i); \
end \
if (is_pc_equal_lpend(hwloop_stat_``TYPE``.hwloop_csr, i, 0, cv32e40p_rvvi_vif.pc_rdata) && hwloop_stat_``TYPE``.track_lp_cnt[i] != 0) begin \
if (pending_irq) lpend_has_pending_irq_``TYPE``[i] = 1; \
// if (pending_irq) lpend_has_pending_irq_``TYPE``[i] = 1; \
if (pending_irq && cv32e40p_rvvi_vif.trap) lpend_has_pending_irq_``TYPE``[i] = 1; \
hwloop_stat_``TYPE``.track_lp_cnt[i]--; \
done_insn_list_capture_``TYPE``[i] = 1; \
assert(hwloop_stat_``TYPE``.track_lp_cnt[i] >= 0); \
Expand Down Expand Up @@ -873,7 +875,7 @@ class uvme_rv32x_hwloop_covg # (
end // IRQ_EXIT
forever begin : SIGNALS_CHG_WHEN_IS_IRQ_ASSERT
@(posedge is_irq);
if (is_ebreakm) begin
if (is_ebreakm) begin // TBD: will ebreakm assert trap?
for (int j=0; j<HWLOOP_NB; j++) begin
logic [31:0] discarded_insn;
if (hwloop_stat_main.execute_instr_in_hwloop[j] && lpend_has_pending_irq_main[j]) begin
Expand Down
10 changes: 5 additions & 5 deletions cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -69,11 +69,11 @@ tests:
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

corev_rand_interrupt_nested:
build: uvmt_cv32e40p
description: corev_rand_interrupt_nested
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=30000000"
# corev_rand_interrupt_nested:
# build: uvmt_cv32e40p
# description: corev_rand_interrupt_nested
# dir: cv32e40p/sim/uvmt
# cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

corev_rand_interrupt_wfi:
build: uvmt_cv32e40p
Expand Down
6 changes: 3 additions & 3 deletions cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -88,12 +88,12 @@ tests:
build: uvmt_cv32e40p
description: pulp_hardware_loop directed test
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=pulp_hardware_loop CFG_PLUSARGS="+UVM_TIMEOUT=1000000" VSIM_USER_FLAGS=+skip_sampling_uvme_rv32x_hwloop_covg
cmd: make test COREV=YES TEST=pulp_hardware_loop CFG_PLUSARGS="+UVM_TIMEOUT=1000000" VSIM_USER_FLAGS="+skip_sampling_uvme_rv32x_hwloop_covg +fixed_data_gnt_stall=3"
num: 1

pulp_hardware_loop_interrupt_test:
build: uvmt_cv32e40p
description: pulp_hardware_loop directed test
description: pulp_hardware_loop_interrupt_test directed test
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=pulp_hardware_loop_interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000"
num: 1
Expand Down Expand Up @@ -136,7 +136,7 @@ tests:

pulp_hardware_loop_debug_test:
build: uvmt_cv32e40p
description: pulp_hardware_loop directed test
description: pulp_hardware_loop_debug_test directed test
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=pulp_hardware_loop_debug_test
num: 1
Expand Down
10 changes: 5 additions & 5 deletions cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do
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Original file line number Diff line number Diff line change
Expand Up @@ -71,18 +71,18 @@ coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_
coverage exclude -line 126 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.}
coverage exclude -line 127 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.}
coverage exclude -line 128 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.}
coverage exclude -line 132 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.}
coverage exclude -line 135 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.}
coverage exclude -line 203 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No cv.elw in this configuration.}
coverage exclude -line 204 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No cv.elw in this configuration.}
coverage exclude -line 321 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Data error not used.}
coverage exclude -line 322 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Data error not used.}
coverage exclude -line 397 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {We are in PULP_OBI == 0 configuration. In this configuration, trans_valid is always asserted when used in this expression.}
coverage exclude -line 132 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.}
coverage exclude -line 135 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.}
coverage exclude -line 155 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.}
coverage exclude -line 295 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.}
coverage exclude -line 2770 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
coverage exclude -line 2768 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
coverage exclude -line 2768 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
coverage exclude -line 2767 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
coverage exclude -line 2765 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
coverage exclude -line 2765 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
coverage exclude -line 419 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. }
coverage exclude -line 451 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. }
coverage exclude -line 452 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. }
Expand Down
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