Merge pull request #2385 from XavierAubert/cv32e40p/dev_dd_w11a

CV32E40Pv2 Verification update

cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv

@@ -832,6 +832,14 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream;
   endfunction: insert_wfi_instr
 
   // add illegal
+  /* Description:
+  *     Directed stream class is to generate a stream of valid riscv_instructions which will be stored in the instr_list.
+  *     In order to insert illegal instruction in directed stream, following is the workaround used in this function.
+  *     - create a valid riscv_instr (it is just a placeholder to allocate a place for illegal instruction insertion).
+  *     - set the helper field "is_illegal_instr" on this valid riscv_instr for post processing of directed stream in cv32e40p_instr_sequence.
+  *     - in sequece, once detected valid riscv_instr with is_illegal_instr==1, it will be replaced with illegal instruction generated from riscv_illegal_instr.
+  *       (note: riscv_illegal_instr which generate a random illegal instruction based on configuration and return it as string)
+  */
   virtual function void insert_illegal_instr();
       riscv_instr illegal_instr;
       illegal_instr = new riscv_instr::get_rand_instr(
@@ -1800,6 +1808,10 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b
             unique case (instr2.category)
               STORE, POST_INC_STORE : begin // S[B|H|WW], C_SW[SP], C_FSW[SP], CV_S[B|H|W]
                         instr2.rs1 = (is_zfinx) ? instr_zfinx.rd : instr_f.rd;
+                        if (instr2.category == POST_INC_STORE && j != num_of_load_store_instr-1) begin // no special handle on last load/store
+                          assert(instr2.has_rd); // rd here is rs3 in spec
+                          instr2.rd = ZERO;      // prevent post incr to update rs1 that target into code space
+                        end
                         last_store_rs1 = instr2.rs1; has_store = 1;
                       end
               LOAD, POST_INC_LOAD : begin // L[B|H|W], C_LW[SP], C_FLW[SP], CV_L[B|H|W|BU|HU]
@@ -1810,6 +1822,10 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b
                           if (instr2.has_rs1 && instr_zfinx.has_rd)   begin instr2.rs1 = instr_zfinx.rd;  last_store_rs1 = instr2.rs1; end
                         end
                         if (instr2.has_rd)                            begin last_load_rd = instr2.rd;     has_load_rd = 1; end
+                        if (instr2.category == POST_INC_LOAD && j != num_of_load_store_instr-1) begin // no special handle on last load/store
+                          assert(instr2.has_rs2);
+                          instr2.rs2 = ZERO;     // prevent post incr to update rs1 that target into code space
+                        end
                         cnt = 0;
                         while (instr2.rd == instr2.rs1) begin
                           int unsigned idx = $urandom_range(avail_gp_regs[i].size()-1);

cv32e40p/env/uvme/uvme_cv32e40p_macros.sv

@@ -27,12 +27,27 @@
 `define APU_INSTR_WITH_NO_FD \
  APU_OP_FCMP, APU_OP_FCLASSIFY, APU_OP_F2I, APU_OP_F2I_U
 
-`define RV32F_INSTR_WITH_NO_FS3 \
- TB_INS_FMADD,TB_INS_FMSUB,TB_INS_FNMSUB,TB_INS_FNMADD
-
 `define RV32_INSTR_WITH_NO_RS2 \
  TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM
 
+`define RV32F_INSTR_WITH_FS1 \
+  TB_INS_FMADD, TB_INS_FNMADD, TB_INS_FMSUB, TB_INS_FNMSUB, TB_INS_FADD, TB_INS_FSUB, TB_INS_FMUL, TB_INS_FDIV, TB_INS_FSQRT, \
+  TB_INS_FSGNJS, TB_INS_FSGNJNS, TB_INS_FSGNJXS, TB_INS_FMIN, TB_INS_FMAX, TB_INS_FCVTWS, TB_INS_FCVTWUS, TB_INS_FMVXS, \
+  TB_INS_FEQS, TB_INS_FLTS, TB_INS_FLES, TB_INS_FCLASS
+
+`define RV32F_INSTR_WITH_FS2 \
+  TB_INS_FMADD, TB_INS_FNMADD, TB_INS_FMSUB, TB_INS_FNMSUB, TB_INS_FADD, TB_INS_FSUB, TB_INS_FMUL, TB_INS_FDIV, \
+  TB_INS_FSGNJS, TB_INS_FSGNJNS, TB_INS_FSGNJXS, TB_INS_FMIN, TB_INS_FMAX, \
+  TB_INS_FEQS, TB_INS_FLTS, TB_INS_FLES
+
+`define RV32F_INSTR_WITH_FS3 \
+  TB_INS_FMADD, TB_INS_FNMADD, TB_INS_FMSUB, TB_INS_FNMSUB
+
+`define RV32F_OP_WITHOUT_FDIV_FSQRT \
+  APU_OP_FMADD, APU_OP_FNMSUB, APU_OP_FADD, APU_OP_FMUL, APU_OP_FSGNJ, APU_OP_FMINMAX, APU_OP_FCMP, \
+  APU_OP_FCLASSIFY, APU_OP_F2I, APU_OP_I2F, APU_OP_FMSUB, APU_OP_FNMADD, APU_OP_FSUB, APU_OP_FSGNJ_SE, \
+  APU_OP_F2I_U, APU_OP_I2F_U
+
 `define RV32F_INSTR_BINS \
  wildcard bins fadd       =    {TB_INS_FADD}; \
  wildcard bins fsub       =    {TB_INS_FSUB}; \
@@ -74,14 +89,12 @@
  wildcard bins fmax       =    {TB_INS_FMAX}; \
  wildcard bins fcvtws     =    {TB_INS_FCVTWS}; \
  wildcard bins fcvtwus    =    {TB_INS_FCVTWUS}; \
- wildcard bins fmvxs      =    {TB_INS_FMVXS}; \
  wildcard bins feqs       =    {TB_INS_FEQS}; \
  wildcard bins flts       =    {TB_INS_FLTS}; \
  wildcard bins fles       =    {TB_INS_FLES}; \
  wildcard bins fclass     =    {TB_INS_FCLASS}; \
  wildcard bins fcvtsw     =    {TB_INS_FCVTSW}; \
  wildcard bins fcvtswu    =    {TB_INS_FCVTSWU}; \
- wildcard bins fmvsw      =    {TB_INS_FMVSX}; \
  wildcard bins fmadd      =    {TB_INS_FMADD}; \
  wildcard bins fmsub      =    {TB_INS_FMSUB}; \
  wildcard bins fnmsub     =    {TB_INS_FNMSUB}; \
@@ -190,7 +203,6 @@
  bins apu_op_fminmax    =    {APU_OP_FMINMAX}; \
  bins apu_op_fcmp       =    {APU_OP_FCMP}; \
  bins apu_op_fclassify  =    {APU_OP_FCLASSIFY}; \
- bins apu_op_f2f        =    {APU_OP_F2F}; \
  bins apu_op_f2i        =    {APU_OP_F2I}; \
  bins apu_op_i2f        =    {APU_OP_I2F}; \
  bins apu_op_fmsub      =    {APU_OP_FMSUB}; \
@@ -199,6 +211,28 @@
  bins apu_op_fsgnj_se   =    {APU_OP_FSGNJ_SE}; \
  bins apu_op_f2i_u      =    {APU_OP_F2I_U}; \
  bins apu_op_i2f_u      =    {APU_OP_I2F_U};
+ // bins apu_op_f2f        =    {APU_OP_F2F}; \ exclude this from above macro because it is for RV32D
+
+`define ZFINX_OP_BINS \
+ bins apu_op_fmadd      =    {APU_OP_FMADD}; \
+ bins apu_op_fnmsub     =    {APU_OP_FNMSUB}; \
+ bins apu_op_fadd       =    {APU_OP_FADD}; \
+ bins apu_op_fmul       =    {APU_OP_FMUL}; \
+ bins apu_op_fdiv       =    {APU_OP_FDIV}; \
+ bins apu_op_fsqrt      =    {APU_OP_FSQRT}; \
+ bins apu_op_fsgnj      =    {APU_OP_FSGNJ}; \
+ bins apu_op_fminmax    =    {APU_OP_FMINMAX}; \
+ bins apu_op_fcmp       =    {APU_OP_FCMP}; \
+ bins apu_op_fclassify  =    {APU_OP_FCLASSIFY}; \
+ bins apu_op_f2i        =    {APU_OP_F2I}; \
+ bins apu_op_i2f        =    {APU_OP_I2F}; \
+ bins apu_op_fmsub      =    {APU_OP_FMSUB}; \
+ bins apu_op_fnmadd     =    {APU_OP_FNMADD}; \
+ bins apu_op_fsub       =    {APU_OP_FSUB}; \
+ bins apu_op_f2i_u      =    {APU_OP_F2I_U}; \
+ bins apu_op_i2f_u      =    {APU_OP_I2F_U};
+ // bins apu_op_fsgnj_se   =    {APU_OP_FSGNJ_SE}; \ exclude this from macro because it is fmv for RV32F
+ // bins apu_op_f2f        =    {APU_OP_F2F};      \ exclude this from above macro because it is for RV32D
 
 `define CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC \
  bins system_opcode          =    {TB_OPCODE_SYSTEM}; \
@@ -224,6 +258,28 @@
  bins xpulp_custom_2         =    {OPCODE_CUSTOM_2}; \
  bins xpulp_custom_3         =    {OPCODE_CUSTOM_3};
 
+`define CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC_FPLS \
+ bins system_opcode          =    {TB_OPCODE_SYSTEM}; \
+ bins fence_opcode           =    {TB_OPCODE_FENCE}; \
+ bins op_opcode              =    {TB_OPCODE_OP}; \
+ bins opimm_opcode           =    {TB_OPCODE_OPIMM}; \
+ bins store_opcode           =    {TB_OPCODE_STORE}; \
+ bins load_opcode            =    {TB_OPCODE_LOAD}; \
+ bins branch_opcode          =    {TB_OPCODE_BRANCH}; \
+ bins jalr_opcode            =    {TB_OPCODE_JALR}; \
+ bins jal_opcode             =    {TB_OPCODE_JAL}; \
+ bins auipc_opcode           =    {TB_OPCODE_AUIPC}; \
+ bins lui_opcode             =    {TB_OPCODE_LUI}; \
+ bins fpu_fp_opcode          =    {TB_OPCODE_OP_FP}; \
+ bins fpu_fmadd_opcode       =    {TB_OPCODE_OP_FMADD}; \
+ bins fpu_fnmadd_opcode      =    {TB_OPCODE_OP_FNMADD}; \
+ bins fpu_fmsub_opcode       =    {TB_OPCODE_OP_FMSUB}; \
+ bins fpu_fnmsub_opcode      =    {TB_OPCODE_OP_FNMSUB}; \
+ bins xpulp_custom_0         =    {OPCODE_CUSTOM_0}; \
+ bins xpulp_custom_1         =    {OPCODE_CUSTOM_1}; \
+ bins xpulp_custom_2         =    {OPCODE_CUSTOM_2}; \
+ bins xpulp_custom_3         =    {OPCODE_CUSTOM_3};
+
 `define RV32X_PULP_INSTR_BINS \
  wildcard bins cv_lb_pi_ri          =    {INSTR_CV_LB_PI_RI}; \
  wildcard bins cv_lh_pi_ri          =    {INSTR_CV_LH_PI_RI}; \

cv32e40p/sim/riscof/config_cv32e40p_v2.ini → cv32e40p/sim/riscof/config_cv32e40p_v2_pulp.ini

@@ -13,7 +13,7 @@ jobs=6
 PATH=riscof
 corevverifPATH=../../../
 imperas_iss=no
-dut_cfg=pulp_fpu
+dut_cfg=pulp
 sw_toolchain_prefix=unknown
 enable_sim_cov=yes
 

cv32e40p/sim/riscof/config_cv32e40p_v2_pulp_fpu.ini

@@ -0,0 +1,29 @@
+[RISCOF]
+ReferencePlugin=sail_cSim
+ReferencePluginPath=./sail_cSim
+DUTPlugin=cv32e40p
+DUTPluginPath=./cv32e40p
+
+[cv32e40p]
+pluginpath=./cv32e40p
+ispec=./cv32e40p/cv32e40p_v2_isa_f.yaml
+pspec=./cv32e40p/cv32e40p_v2_platform.yaml
+target_run=1
+jobs=6
+PATH=riscof
+corevverifPATH=../../../
+imperas_iss=no
+dut_cfg=pulp_fpu
+sw_toolchain_prefix=unknown
+enable_sim_cov=yes
+
+[sail_cSim]
+pluginpath=./sail_cSim
+#docker=True
+image=registry.gitlab.com/incoresemi/docker-images/compliance
+target_run=1
+jobs=1
+#PATH=/usr/bin/
+make=make
+sw_toolchain_prefix=unknown
+

cv32e40p/sim/riscof/config_cv32e40p_v2_pulp_fpu_1cyclat.ini

@@ -6,15 +6,15 @@ DUTPluginPath=./cv32e40p
 
 [cv32e40p]
 pluginpath=./cv32e40p
-ispec=./cv32e40p/cv32e40p_v2_isa.yaml
+ispec=./cv32e40p/cv32e40p_v2_isa_f.yaml
 pspec=./cv32e40p/cv32e40p_v2_platform.yaml
 target_run=1
-jobs=4
+jobs=6
 PATH=riscof
 corevverifPATH=../../../
-imperas_iss=yes
+imperas_iss=no
 dut_cfg=pulp_fpu_1cyclat
-sw_toolchain_prefix=corev
+sw_toolchain_prefix=unknown
 enable_sim_cov=yes
 
 [sail_cSim]
@@ -25,5 +25,5 @@ target_run=1
 jobs=1
 #PATH=/usr/bin/
 make=make
-sw_toolchain_prefix=corev
+sw_toolchain_prefix=unknown
 

cv32e40p/sim/riscof/config_cv32e40p_v2_pulp_fpu_2cyclat.ini

@@ -6,15 +6,15 @@ DUTPluginPath=./cv32e40p
 
 [cv32e40p]
 pluginpath=./cv32e40p
-ispec=./cv32e40p/cv32e40p_v2_isa.yaml
+ispec=./cv32e40p/cv32e40p_v2_isa_f.yaml
 pspec=./cv32e40p/cv32e40p_v2_platform.yaml
 target_run=1
-jobs=4
+jobs=6
 PATH=riscof
 corevverifPATH=../../../
-imperas_iss=yes
+imperas_iss=no
 dut_cfg=pulp_fpu_2cyclat
-sw_toolchain_prefix=corev
+sw_toolchain_prefix=unknown
 enable_sim_cov=yes
 
 [sail_cSim]
@@ -25,5 +25,5 @@ target_run=1
 jobs=1
 #PATH=/usr/bin/
 make=make
-sw_toolchain_prefix=corev
+sw_toolchain_prefix=unknown
 

cv32e40p/sim/riscof/cv32e40p/cv32e40p_v2_isa.yaml

@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMFCZicsr_Zifencei
+  ISA: RV32IMCZicsr_Zifencei
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   Privilege_Spec_Version: '1.11'

cv32e40p/sim/riscof/cv32e40p/cv32e40p_v2_isa_f.yaml

@@ -0,0 +1,60 @@
+hart_ids: [0]
+hart0:
+  ISA: RV32IMFCZicsr_Zifencei
+  physical_addr_sz: 32
+  User_Spec_Version: '2.3'
+  Privilege_Spec_Version: '1.11'
+  pmp_granularity: 0
+  supported_xlen: [32]
+  hw_data_misaligned_support: True
+  mtval_update: 0x00000000
+  mcause:
+    reset-val: 0x00000000
+    rv32:
+      accessible: true
+      interrupt:
+        implemented: true
+        type:
+          wlrl: [0x0:0x1]
+        msb: 31
+        lsb: 31
+      exception_code:
+        implemented: true
+        type:
+          wlrl:
+            - 0:31
+        msb: 30
+        lsb: 0
+  mtvec:
+    reset-val: 0x00000001
+    rv32:
+      accessible: true
+      base:
+        implemented: true
+        type:
+          warl:
+            dependency_fields: []
+            legal:
+              - "base[29:6] in [0x000000:0xFFFFFF] base[5:0] in [0x00]"
+            wr_illegal:
+              - "Unchanged"
+      mode:
+        implemented: true
+        type:
+          warl:
+            dependency_fields: []
+            legal:
+              - "mode[1:0] in [0x0:0x1]"
+            wr_illegal:
+              - "Unchanged"
+  mtval:
+    reset-val: 0x00000000
+    rv32:
+      accessible: true
+      type:
+        warl:
+          dependency_fields: []
+          legal:
+            - "mtval[31:0] in [0x00000000]"
+          wr_illegal:
+            - "Unchanged"

cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do

@@ -42,12 +42,8 @@ coverage exclude -line 212 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb
 coverage exclude -line 163 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.}
 coverage exclude -line 174 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.}
 coverage exclude -line 185 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.}
-coverage exclude -line 212 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {Hidden by branch line 205.}
-coverage exclude -line 211 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {Hidden by branch line 205.}
 coverage exclude -line 460 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {We dont support OBI error.}
 coverage exclude -line 459 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {We dont support OBI error.}
-coverage exclude -line 211 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {Hidden by branch line 205.}
-coverage exclude -line 211 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {Hidden by branch line 205.}
 coverage exclude -line 549 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.}
 coverage exclude -line 579 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.}
 coverage exclude -line 608 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.}
@@ -58,6 +54,7 @@ coverage exclude -line 528 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb
 coverage exclude -line 645 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {IMB_S3 never exists in the decoder. This is unreachable.}
 coverage exclude -line 528 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {reg_c = S1 never exist in the decoder. This is unreachable.}
 coverage exclude -line 645 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {IMB_S3 never exists in the decoder. This is unreachable.}
+coverage exclude -line 724 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {scalar_replication_c is never asserted. Can olny be asserted for vector float instruction. Unreachable in all conf we verify for v2. Reachable only in vector conf.}
 coverage exclude -line 362 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i -comment {No user mode in this configuration.}
 coverage exclude -line 362 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i -comment {No user mode in this configuration. }
 coverage exclude -line 81 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never overflow the fifo.}

cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do

@@ -0,0 +1,9 @@
+coverage exclude -line 1269 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported}
+coverage exclude -line 1270 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported}
+coverage exclude -line 1271 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported}
+coverage exclude -line 1278 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported}
+coverage exclude -line 1279 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported}
+coverage exclude -line 1280 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported}
+coverage exclude -line 1300 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported}
+coverage exclude -line 1301 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported}
+coverage exclude -line 1302 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported}