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Add RTL code coverage waiver for some instances in FPU
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Signed-off-by: Bee Nee Lim <[email protected]>
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@dd-BeeNee
dd-BeeNee committed May 31, 2024
1 parent bda6e3e commit 48ac67c
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8 changes: 8 additions & 0 deletions cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do
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Expand Up @@ -43,6 +43,7 @@ coverage exclude -line 59 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb
coverage exclude -line 59 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV}
coverage exclude -line 59 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV}
coverage exclude -line 59 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV}
coverage exclude -line 73 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {effective_substraction_i is stuck at 0.}
coverage exclude -line 148 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_decode_rm is never 7. This correspond to DYN rounding mode.}
coverage exclude -line 149 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_decode_rm is never 7. This correspond to DYN rounding mode.}
coverage exclude -line 155 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_src2_vld never asserted. This is expression 151.}
Expand Down Expand Up @@ -248,6 +249,13 @@ coverage exclude -line 208 -code b -allfalse -scope {/uvmt_cv32e40p_tb/dut_wrap/
coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.}
coverage exclude -line 209 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.}
coverage exclude -line 213 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {We never use cast and pack.}
coverage exclude -line 131 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice} -comment {We never have dst_fmt_is_int for this op group. This is the DIVSQRT opGroup and dst_fmt_is_int can only be asserted for the CONV opGroup.}
coverage exclude -line 194 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {This is use to manage all operands. In the DIVSQRT op group we have only 2 operands.}
coverage exclude -feccondrow 194 2 -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice} -comment {This is use to manage all operands. In the DIVSQRT op group we have only 2 operands.}
coverage exclude -line 195 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {Statement hidden by previous line.}
coverage exclude -line 503 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice} -comment {We never have result_fmt_is_int for this op group. This is the DIVSQRT opGroup and result_fmt_is_int can only be asserted for the CONV opGroup.}
coverage exclude -line 131 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice} -comment {We never have dst_fmt_is_int for this op group. This is the ADMUL opGroup and dst_fmt_is_int can only be asserted for the CONV opGroup.}
coverage exclude -line 503 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice} -comment {We never have result_fmt_is_int for this op group. This is the ADMUL opGroup and result_fmt_is_int can only be asserted for the CONV opGroup.}
coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.}
coverage exclude -line 243 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.}
coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.}
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