Merge pull request #2219 from silabs-hfegran/dev_hf_dis_xsec

Added cfg to disable data independent timing and pc hardening

cv32e40s/env/corev-dv/cv32e40s_asm_program_gen.sv

@@ -43,30 +43,60 @@ class cv32e40s_asm_program_gen extends corev_asm_program_gen;
       end
       2'b01: begin
         instr = {
-          $sformatf("add x%0d, zero", cfg.gpr[0]),
-          $sformatf("addi x%0d, 0x4", cfg.gpr[0]),
+          $sformatf("lui x%0d, 0x0", cfg.gpr[0]),
+          $sformatf("ori x%0d, x%0d, 0x4", cfg.gpr[0], cfg.gpr[0]),
           $sformatf("csrrs x0, 0xbf0, x%0d", cfg.gpr[0])
         };
         gen_section(get_label("enable_hint_instr", hart), instr);
       end
       2'b10: begin
         instr = {
           $sformatf("lui x%0d, 0xf0", cfg.gpr[0]),
-          $sformatf("addi x%0d, x%0d, 0x2", cfg.gpr[0], cfg.gpr[0]),
+          $sformatf("ori x%0d, x%0d, 0x2", cfg.gpr[0], cfg.gpr[0]),
           $sformatf("csrrs x0, 0xbf0, x%0d", cfg.gpr[0])
         };
         gen_section(get_label("enable_dummy_instr", hart), instr);
       end
       2'b11: begin
         instr = {
           $sformatf("lui x%0d, 0xf0", cfg.gpr[0]),
-          $sformatf("addi x%0d, x%0d, 0x6", cfg.gpr[0], cfg.gpr[0]),
+          $sformatf("ori x%0d, x%0d, 0x6", cfg.gpr[0], cfg.gpr[0]),
           $sformatf("csrrs x0, 0xbf0, x%0d", cfg.gpr[0])
         };
         gen_section(get_label("enable_dummy_hint_instr", hart), instr);
       end
     endcase
 
+    case ({corev_cfg.disable_pc_hardening, corev_cfg.disable_data_independent_timing})
+      2'b00: begin
+        // Nothing disabled
+      end
+      2'b01: begin
+        instr = {
+          $sformatf("lui x%0d, 0", cfg.gpr[0]),
+          $sformatf("ori x%0d, x%0d, 0x1", cfg.gpr[0], cfg.gpr[0]),
+          $sformatf("csrrc x0, 0xbf0, x%0d", cfg.gpr[0])
+        };
+        gen_section(get_label("disable_pc_hardening_data_ind_timing", hart), instr);
+      end
+      2'b10: begin
+        instr = {
+          $sformatf("lui x%0d, 0", cfg.gpr[0]),
+          $sformatf("ori x%0d, x%0d, 0x8", cfg.gpr[0], cfg.gpr[0]),
+          $sformatf("csrrc x0, 0xbf0, x%0d", cfg.gpr[0])
+        };
+        gen_section(get_label("disable_pc_hardening_data_ind_timing", hart), instr);
+      end
+      2'b11: begin
+        instr = {
+          $sformatf("lui x%0d, 0", cfg.gpr[0]),
+          $sformatf("ori x%0d, x%0d, 0x9", cfg.gpr[0], cfg.gpr[0]),
+          $sformatf("csrrc x0, 0xbf0, x%0d", cfg.gpr[0])
+        };
+        gen_section(get_label("disable_pc_hardening_data_ind_timing", hart), instr);
+      end
+    endcase
+
   endfunction : gen_program_header
 
   virtual function void trap_vector_init(int hart);

cv32e40s/env/corev-dv/cv32e40s_instr_gen_config.sv

@@ -29,6 +29,8 @@ class cv32e40s_instr_gen_config extends riscv_instr_gen_config;
   bit enable_pma;
   bit enable_dummy;
   bit enable_hint;
+  bit disable_pc_hardening;
+  bit disable_data_independent_timing;
   bit exit_on_debug_exception;
   cv32e40s_pma_cfg pma_cfg;
 
@@ -87,16 +89,18 @@ class cv32e40s_instr_gen_config extends riscv_instr_gen_config;
   }
 
   `uvm_object_utils_begin(cv32e40s_instr_gen_config)
-    `uvm_field_enum(mtvec_mode_t, mtvec_mode,     UVM_DEFAULT)
-    `uvm_field_enum(riscv_reg_t, dp,              UVM_DEFAULT)
-    `uvm_field_enum(riscv_reg_t, scratch_reg,     UVM_DEFAULT)
-    `uvm_field_int(knob_zero_fast_intr_handlers,  UVM_DEFAULT)
-    `uvm_field_int(enable_fast_interrupt_handler, UVM_DEFAULT)
-    `uvm_field_int(use_fast_intr_handler,         UVM_DEFAULT)
-    `uvm_field_int(enable_pma,                    UVM_DEFAULT)
-    `uvm_field_int(exit_on_debug_exception,       UVM_DEFAULT)
-    `uvm_field_int(enable_dummy,                  UVM_DEFAULT)
-    `uvm_field_int(enable_hint,                   UVM_DEFAULT)
+    `uvm_field_enum(mtvec_mode_t, mtvec_mode,       UVM_DEFAULT)
+    `uvm_field_enum(riscv_reg_t, dp,                UVM_DEFAULT)
+    `uvm_field_enum(riscv_reg_t, scratch_reg,       UVM_DEFAULT)
+    `uvm_field_int(knob_zero_fast_intr_handlers,    UVM_DEFAULT)
+    `uvm_field_int(enable_fast_interrupt_handler,   UVM_DEFAULT)
+    `uvm_field_int(use_fast_intr_handler,           UVM_DEFAULT)
+    `uvm_field_int(enable_pma,                      UVM_DEFAULT)
+    `uvm_field_int(exit_on_debug_exception,         UVM_DEFAULT)
+    `uvm_field_int(enable_dummy,                    UVM_DEFAULT)
+    `uvm_field_int(enable_hint,                     UVM_DEFAULT)
+    `uvm_field_int(disable_pc_hardening,            UVM_DEFAULT)
+    `uvm_field_int(disable_data_independent_timing, UVM_DEFAULT)
   `uvm_object_utils_end
 
   function new(string name="");
@@ -107,6 +111,8 @@ class cv32e40s_instr_gen_config extends riscv_instr_gen_config;
     get_bool_arg_value("+exit_on_debug_exception=", exit_on_debug_exception);
     get_bool_arg_value("+enable_dummy=", enable_dummy);
     get_bool_arg_value("+enable_hint=", enable_hint);
+    get_bool_arg_value("+disable_pc_hardening=", disable_pc_hardening);
+    get_bool_arg_value("+disable_data_independent_timing=", disable_data_independent_timing);
 
     if (enable_pma) begin
       pma_cfg = cv32e40s_pma_cfg::type_id::create("pma_cfg");

cv32e40s/regress/cv32e40s_full.yaml

@@ -104,6 +104,11 @@ builds:
     cfg: debug_trigger_cfg4
     dir: cv32e40s/sim/uvmt
 
+  uvmt_cv32e40s_xsecure_disable_std:
+    cmd: make comp_corev-dv comp
+    cfg: xsecure_disable_std
+    dir: cv32e40s/sim/uvmt
+
 
 # List of tests
 tests:
@@ -207,14 +212,14 @@ tests:
 
   corev_rand_arithmetic_base_test:
     description: Generated corev-dv arithmetic test
-    builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr]
+    builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_xsecure_disable_std ]
     dir: cv32e40s/sim/uvmt
     cmd: make gen_corev-dv test TEST=corev_rand_arithmetic_base_test
     num: 4
 
   corev_rand_instr_test:
     description: Generated corev-dv random instruction test
-    builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr]
+    builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_xsecure_disable_std ]
     dir: cv32e40s/sim/uvmt
     cmd: make gen_corev-dv test TEST=corev_rand_instr_test
     num: 5

cv32e40s/tests/cfg/xsecure_disable_std.yaml

@@ -0,0 +1,202 @@
+name: xsecure_disable_std
+description: Default configuration for CV32E40S random simulations that includes dummy instructions but disables pc hardening and data independent timing features
+compile_flags:
+    +define+ZBA_ZBB_ZBC_ZBS
+    +define+CLIC_EN
+    +define+PMP_ENABLE_64
+    +define+LFSR_CFG_0
+plusargs: >
+    +enable_clic=1
+    +enable_zba_extension=1
+    +enable_zbb_extension=1
+    +enable_zbc_extension=1
+    +enable_zbs_extension=1
+    +fix_sp=1
+    +fix_ra=1
+    +enable_zca_extension=1
+    +enable_zcb_extension=1
+    +enable_zcmt_extension=1
+    +enable_zcmp_extension=1
+    +enable_dummy=1
+    +enable_hint=1
+    +disable_data_independent_timing=1
+    +disable_pc_hardening=1
+ovpsim: >
+    --override cpu/CLICLEVELS=256
+    --override cpu/CLICXCSW=T
+    --override cpu/CLICXNXTI=T
+    --override cpu/CLICSELHVEC=T
+    --override cpu/CLICINTCTLBITS=8
+    --override cpu/CLIC_version=master
+    --override cpu/externalCLIC=T
+    --override cpu/mtvt_mask=0xffffffffffffff80
+    --override cpu/PMP_registers=64
+    --override cpu/PMP_registers=64
+    --override cpu/PMP_undefined=T
+    --override cpu/PMP_initialparams=T
+    --override cpu/PMP_maskparams=T
+    --override cpu/pmpaddr0=0
+    --override cpu/pmpaddr1=0
+    --override cpu/pmpaddr2=0
+    --override cpu/pmpaddr3=0
+    --override cpu/pmpaddr4=0
+    --override cpu/pmpaddr5=0
+    --override cpu/pmpaddr6=0
+    --override cpu/pmpaddr7=0
+    --override cpu/pmpaddr8=0
+    --override cpu/pmpaddr9=0
+    --override cpu/pmpaddr10=0
+    --override cpu/pmpaddr11=0
+    --override cpu/pmpaddr12=0
+    --override cpu/pmpaddr13=0
+    --override cpu/pmpaddr14=0
+    --override cpu/pmpaddr15=0
+    --override cpu/pmpaddr16=0
+    --override cpu/pmpaddr17=0
+    --override cpu/pmpaddr18=0
+    --override cpu/pmpaddr19=0
+    --override cpu/pmpaddr20=0
+    --override cpu/pmpaddr21=0
+    --override cpu/pmpaddr22=0
+    --override cpu/pmpaddr23=0
+    --override cpu/pmpaddr24=0
+    --override cpu/pmpaddr25=0
+    --override cpu/pmpaddr26=0
+    --override cpu/pmpaddr27=0
+    --override cpu/pmpaddr28=0
+    --override cpu/pmpaddr29=0
+    --override cpu/pmpaddr30=0
+    --override cpu/pmpaddr31=0
+    --override cpu/pmpaddr32=0
+    --override cpu/pmpaddr33=0
+    --override cpu/pmpaddr34=0
+    --override cpu/pmpaddr35=0
+    --override cpu/pmpaddr36=0
+    --override cpu/pmpaddr37=0
+    --override cpu/pmpaddr38=0
+    --override cpu/pmpaddr39=0
+    --override cpu/pmpaddr40=0
+    --override cpu/pmpaddr41=0
+    --override cpu/pmpaddr42=0
+    --override cpu/pmpaddr43=0
+    --override cpu/pmpaddr44=0
+    --override cpu/pmpaddr45=0
+    --override cpu/pmpaddr46=0
+    --override cpu/pmpaddr47=0
+    --override cpu/pmpaddr48=0
+    --override cpu/pmpaddr49=0
+    --override cpu/pmpaddr50=0
+    --override cpu/pmpaddr51=0
+    --override cpu/pmpaddr52=0
+    --override cpu/pmpaddr53=0
+    --override cpu/pmpaddr54=0
+    --override cpu/pmpaddr55=0
+    --override cpu/pmpaddr56=0
+    --override cpu/pmpaddr57=0
+    --override cpu/pmpaddr58=0
+    --override cpu/pmpaddr59=0
+    --override cpu/pmpaddr60=0
+    --override cpu/pmpaddr61=0
+    --override cpu/pmpaddr62=0
+    --override cpu/pmpaddr63=0
+    --override cpu/pmpcfg0=0
+    --override cpu/pmpcfg1=0
+    --override cpu/pmpcfg2=0
+    --override cpu/pmpcfg3=0
+    --override cpu/pmpcfg4=0
+    --override cpu/pmpcfg5=0
+    --override cpu/pmpcfg6=0
+    --override cpu/pmpcfg7=0
+    --override cpu/pmpcfg8=0
+    --override cpu/pmpcfg9=0
+    --override cpu/pmpcfg10=0
+    --override cpu/pmpcfg11=0
+    --override cpu/pmpcfg12=0
+    --override cpu/pmpcfg13=0
+    --override cpu/pmpcfg14=0
+    --override cpu/pmpcfg15=0
+    --override cpu/mask_pmpaddr0=0x00000000
+    --override cpu/mask_pmpaddr1=0x00000000
+    --override cpu/mask_pmpaddr2=0x00000000
+    --override cpu/mask_pmpaddr3=0x00000000
+    --override cpu/mask_pmpaddr4=0x00000000
+    --override cpu/mask_pmpaddr5=0x00000000
+    --override cpu/mask_pmpaddr6=0x00000000
+    --override cpu/mask_pmpaddr7=0x00000000
+    --override cpu/mask_pmpaddr8=0x00000000
+    --override cpu/mask_pmpaddr9=0x00000000
+    --override cpu/mask_pmpaddr10=0x00000000
+    --override cpu/mask_pmpaddr11=0x00000000
+    --override cpu/mask_pmpaddr12=0x00000000
+    --override cpu/mask_pmpaddr13=0x00000000
+    --override cpu/mask_pmpaddr14=0x00000000
+    --override cpu/mask_pmpaddr15=0x00000000
+    --override cpu/mask_pmpaddr16=0x00000000
+    --override cpu/mask_pmpaddr17=0x00000000
+    --override cpu/mask_pmpaddr18=0x00000000
+    --override cpu/mask_pmpaddr19=0x00000000
+    --override cpu/mask_pmpaddr20=0x00000000
+    --override cpu/mask_pmpaddr21=0x00000000
+    --override cpu/mask_pmpaddr22=0x00000000
+    --override cpu/mask_pmpaddr23=0x00000000
+    --override cpu/mask_pmpaddr24=0x00000000
+    --override cpu/mask_pmpaddr25=0x00000000
+    --override cpu/mask_pmpaddr26=0x00000000
+    --override cpu/mask_pmpaddr27=0x00000000
+    --override cpu/mask_pmpaddr28=0x00000000
+    --override cpu/mask_pmpaddr29=0x00000000
+    --override cpu/mask_pmpaddr30=0x00000000
+    --override cpu/mask_pmpaddr31=0x00000000
+    --override cpu/mask_pmpaddr32=0x00000000
+    --override cpu/mask_pmpaddr33=0x00000000
+    --override cpu/mask_pmpaddr34=0x00000000
+    --override cpu/mask_pmpaddr35=0x00000000
+    --override cpu/mask_pmpaddr36=0x00000000
+    --override cpu/mask_pmpaddr37=0x00000000
+    --override cpu/mask_pmpaddr38=0x00000000
+    --override cpu/mask_pmpaddr39=0x00000000
+    --override cpu/mask_pmpaddr40=0x00000000
+    --override cpu/mask_pmpaddr41=0x00000000
+    --override cpu/mask_pmpaddr42=0x00000000
+    --override cpu/mask_pmpaddr43=0x00000000
+    --override cpu/mask_pmpaddr44=0x00000000
+    --override cpu/mask_pmpaddr45=0x00000000
+    --override cpu/mask_pmpaddr46=0x00000000
+    --override cpu/mask_pmpaddr47=0x00000000
+    --override cpu/mask_pmpaddr48=0x00000000
+    --override cpu/mask_pmpaddr49=0x00000000
+    --override cpu/mask_pmpaddr50=0x00000000
+    --override cpu/mask_pmpaddr51=0x00000000
+    --override cpu/mask_pmpaddr52=0x00000000
+    --override cpu/mask_pmpaddr53=0x00000000
+    --override cpu/mask_pmpaddr54=0x00000000
+    --override cpu/mask_pmpaddr55=0x00000000
+    --override cpu/mask_pmpaddr56=0x00000000
+    --override cpu/mask_pmpaddr57=0x00000000
+    --override cpu/mask_pmpaddr58=0x00000000
+    --override cpu/mask_pmpaddr59=0x00000000
+    --override cpu/mask_pmpaddr60=0x00000000
+    --override cpu/mask_pmpaddr61=0x00000000
+    --override cpu/mask_pmpaddr62=0x00000000
+    --override cpu/mask_pmpaddr63=0x00000000
+    --override cpu/mask_pmpcfg0=0x00000000
+    --override cpu/mask_pmpcfg1=0x00000000
+    --override cpu/mask_pmpcfg2=0x00000000
+    --override cpu/mask_pmpcfg3=0x00000000
+    --override cpu/mask_pmpcfg4=0x00000000
+    --override cpu/mask_pmpcfg5=0x00000000
+    --override cpu/mask_pmpcfg6=0x00000000
+    --override cpu/mask_pmpcfg7=0x00000000
+    --override cpu/mask_pmpcfg8=0x00000000
+    --override cpu/mask_pmpcfg9=0x00000000
+    --override cpu/mask_pmpcfg10=0x00000000
+    --override cpu/mask_pmpcfg11=0x00000000
+    --override cpu/mask_pmpcfg12=0x00000000
+    --override cpu/mask_pmpcfg13=0x00000000
+    --override cpu/mask_pmpcfg14=0x00000000
+    --override cpu/mask_pmpcfg15=0x00000000
+    # --showoverrides
+    # --trace --tracechange --traceshowicount --monitornets
+cflags: >
+    -Wl,--nmagic
+cv_sw_march: rv32im_zicsr_zba1p00_zbb1p00_zbc1p00_zbs1p00_zca_zcb_zcmp_zcmt_zifencei