Merge pull request #1891 from pascalgouedo/cv32e40p/dev_pgo_zfinx

Test-bench and scripts updates to align to CV32E40P PR ...
openhwgroup · May 12, 2023 · 0206595 · 0206595
2 parents f24f40e + a110cb5
commit 0206595
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Showing 64 changed files with 197 additions and 699 deletions.
diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv
@@ -291,11 +291,6 @@ function void uvme_cv32e40p_cfg_c::pre_randomize();
       zero_stall_sim = 1;
       zero_stall_sim.rand_mode(0);
 
-      // Hack-set is_stall_sim bit in step_compare
-      retval = uvm_hdl_deposit("uvmt_cv32e40p_tb.step_compare.is_stall_sim", 0);
-      if (!retval) begin
-         `uvm_fatal("ZEROSTALL", "Cannot set is_stall_sim in step_compare")
-      end
    end
    else if ($test$plusargs("max_data_zero_instr_stall")) begin
       // No stalls on the I bus, max on D bus

diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk
@@ -15,10 +15,9 @@ export SHELL = /bin/bash
 
 CV_CORE_REPO   ?= https://github.com/openhwgroup/cv32e40p
 CV_CORE_BRANCH ?= dev
-CV_CORE_HASH   ?= f08fe74f8cfacda5ec6883adc689e827ea562ca7
+CV_CORE_HASH   ?= 4d960913d69e2043df80ac249ea17a008b67aaa6
 CV_CORE_TAG    ?= none
 
-
 # The CV_CORE_HASH above points to version of the RTL that is newer.
 # It is logically equivalent with respect to v1.0.0 RTL freeze version with all parameters disabled.
 # There are some implementation and testbench updates in the above hash.

diff --git a/cv32e40p/sim/uvmt/Makefile b/cv32e40p/sim/uvmt/Makefile
@@ -49,8 +49,6 @@ export CORE_V_VERIF   = $(abspath $(MAKE_PATH)/../../..)
 export CV_CORE       ?= cv32e40p
 
 DPI_DASM_SPIKE_REPO  ?= https://github.com/riscv/riscv-isa-sim.git
-CV_SW_TOOLCHAIN      ?= /opt/riscv
-CV_SW_PREFIX         ?= " "
 
 include ../ExternalRepos.mk
 include $(CORE_V_VERIF)/mk/uvmt/uvmt.mk
diff --git a/cv32e40p/tb/core/cv32e40p_tb_wrapper.sv b/cv32e40p/tb/core/cv32e40p_tb_wrapper.sv
@@ -23,10 +23,10 @@ module cv32e40p_tb_wrapper
                 DM_HALTADDRESS    = 32'h1A11_0800,
                 HART_ID           = 32'h0000_0000,
                 // Parameters used by DUT
-                PULP_XPULP        = 0,
-                PULP_CLUSTER      = 0,
+                COREV_PULP        = 0,
+                COREV_CLUSTER     = 0,
                 FPU               = 0,
-                PULP_ZFINX        = 0,
+                ZFINX             = 0,
                 NUM_MHPMCOUNTERS  = 1
     )
     (input logic         clk_i,
@@ -72,10 +72,10 @@ module cv32e40p_tb_wrapper
 //    // MIKET: commenting out as the cv32e40p RTL wrapper does this as well.
 //    cv32e40p_core_log
 //     #(
-//          .PULP_XPULP            ( PULP_XPULP            ),
-//          .PULP_CLUSTER          ( PULP_CLUSTER          ),
+//          .COREV_PULP            ( COREV_PULP            ),
+//          .COREV_CLUSTER         ( COREV_CLUSTER         ),
 //          .FPU                   ( FPU                   ),
-//          .PULP_ZFINX            ( PULP_ZFINX            ),
+//          .ZFINX                 ( ZFINX                 ),
 //          .NUM_MHPMCOUNTERS      ( NUM_MHPMCOUNTERS      ))
 //    core_log_i(
 //          .clk_i              ( cv32e40p_core_i.id_stage_i.clk              ),
@@ -87,10 +87,10 @@ module cv32e40p_tb_wrapper
 
     // instantiate the core
     cv32e40p_core #(
-                 .PULP_XPULP       (PULP_XPULP),
-                 .PULP_CLUSTER     (PULP_CLUSTER),
+                 .COREV_PULP       (COREV_PULP),
+                 .COREV_CLUSTER    (COREV_CLUSTER),
                  .FPU              (FPU),
-                 .PULP_ZFINX       (PULP_ZFINX),
+                 .ZFINX            (ZFINX),
                  .NUM_MHPMCOUNTERS (NUM_MHPMCOUNTERS)
                 )
     cv32e40p_core_i

diff --git a/cv32e40p/tb/core/tb_riscv/tb_riscv_core.sv b/cv32e40p/tb/core/tb_riscv/tb_riscv_core.sv
@@ -34,7 +34,7 @@ module tb_riscv_core
   parameter INSTR_RDATA_WIDTH   = 32,
   parameter PULP_SECURE         =  0,
   parameter N_PMP_ENTRIES       = 16,
-  parameter PULP_CLUSTER        =  1,
+  parameter COREV_CLUSTER       =  1,
   parameter FPU                 =  0,
   parameter SHARED_FP           =  0,
   parameter SHARED_DSP_MULT     =  0,

diff --git a/cv32e40p/tb/core/tb_top_verilator.sv b/cv32e40p/tb/core/tb_top_verilator.sv
@@ -89,9 +89,9 @@ module tb_top_verilator
         #(.INSTR_RDATA_WIDTH (INSTR_RDATA_WIDTH),
           .RAM_ADDR_WIDTH    (RAM_ADDR_WIDTH),
           .BOOT_ADDR         (BOOT_ADDR),
-          .PULP_CLUSTER      (0),
+          .COREV_CLUSTER     (0),
           .FPU               (0),
-          .PULP_ZFINX        (0),
+          .ZFINX             (0),
           .DM_HALTADDRESS    (32'h1A110800)
          )
     cv32e40p_tb_wrapper_i

diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv
@@ -42,12 +42,12 @@
 module uvmt_cv32e40p_dut_wrap 
   #(
                             // CV32E40P parameters.  See User Manual.
-                            parameter PULP_XPULP          =  0,
-                                      PULP_CLUSTER        =  0,
+                            parameter COREV_PULP          =  0,
+                                      COREV_CLUSTER       =  0,
                                       FPU                 =  0,
                                       FPU_ADDMUL_LAT      =  0,
                                       FPU_OTHERS_LAT      =  0,
-                                      PULP_ZFINX          =  0,
+                                      ZFINX               =  0,
                                       NUM_MHPMCOUNTERS    =  1,
                             // Remaining parameters are used by TB components only
                                       INSTR_ADDR_WIDTH    =  32,
@@ -136,12 +136,12 @@ module uvmt_cv32e40p_dut_wrap
     // -------------------------------------------------------------
     // Instantiate the Core and optional FPU plus logger and tracers
     cv32e40p_tb_wrapper #(
-                 .PULP_XPULP       (PULP_XPULP),
-                 .PULP_CLUSTER     (PULP_CLUSTER),
+                 .COREV_PULP       (COREV_PULP),
+                 .COREV_CLUSTER    (COREV_CLUSTER),
                  .FPU              (FPU),
                  .FPU_ADDMUL_LAT   (FPU_ADDMUL_LAT),
                  .FPU_OTHERS_LAT   (FPU_OTHERS_LAT),
-                 .PULP_ZFINX       (PULP_ZFINX),
+                 .ZFINX            (ZFINX),
                  .NUM_MHPMCOUNTERS (NUM_MHPMCOUNTERS)
                 )
     cv32e40p_tb_wrapper_i

diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv
@@ -477,10 +477,6 @@ module uvmt_cv32e40p_imperas_dv_wrap
 
     // TODO silabs-hfegran: temp fix to work around issues
     // rvviRefCsrCompareEnable(hart_id, `CSR_DCSR_ADDR,   RVVI_FALSE);
-
-    // rvviRefCsrCompareEnable(hart_id, `CSR_MSTATUS_ADDR,   RVVI_FALSE);
-    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MSTATUS_ADDR          ));
-    rvviRefCsrCompareEnable(hart_id, `CSR_MISA_ADDR,   RVVI_FALSE);
     // end TODO
     // define asynchronous grouping
     // Interrupts
@@ -504,7 +500,7 @@ module uvmt_cv32e40p_imperas_dv_wrap
     rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt14"),    1);
     rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt15"),    1);
 
-    rvviRefNetGroupSet(rvviRefNetIndexGet("InstructionBusFault"), 2);
+//  rvviRefNetGroupSet(rvviRefNetIndexGet("InstructionBusFault"), 2);
 
     // Debug
     rvviRefNetGroupSet(rvviRefNetIndexGet("haltreq"),             4);