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riscv: Fix SMP when shadow call stacks are enabled
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This fixes two bugs in SCS initialization for secondary CPUs. First,
the SCS was not initialized at all in the spinwait boot path. Second,
the code for the SBI HSM path attempted to initialize the SCS before
enabling the MMU. However, that involves dereferencing the thread
pointer, which requires the MMU to be enabled.

Fix both issues by setting up the SCS in the common secondary entry
path, after enabling the MMU.

Fixes: d1584d7 ("riscv: Implement Shadow Call Stack")
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Sami Tolvanen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
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SiFiveHolland authored and palmer-dabbelt committed Dec 6, 2023
1 parent 96ba4a4 commit f40cab8
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion arch/riscv/kernel/head.S
Original file line number Diff line number Diff line change
Expand Up @@ -154,7 +154,6 @@ secondary_start_sbi:
XIP_FIXUP_OFFSET a3
add a3, a3, a1
REG_L sp, (a3)
scs_load_current

.Lsecondary_start_common:

Expand All @@ -165,6 +164,7 @@ secondary_start_sbi:
call relocate_enable_mmu
#endif
call .Lsetup_trap_vector
scs_load_current
tail smp_callin
#endif /* CONFIG_SMP */

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