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feat: update acvm to 0.15.1 #1764

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Jun 21, 2023
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21 changes: 10 additions & 11 deletions Cargo.lock

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2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ edition = "2021"
rust-version = "1.66"

[workspace.dependencies]
acvm = "0.15.0"
acvm = "0.15.1"
arena = { path = "crates/arena" }
fm = { path = "crates/fm" }
iter-extended = { path = "crates/iter-extended" }
Expand Down
19 changes: 8 additions & 11 deletions crates/nargo/src/ops/execute.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@
use acvm::acir::brillig_vm::ForeignCallResult;
use acvm::acir::circuit::Opcode;
use acvm::pwg::{solve, Blocks, PartialWitnessGeneratorStatus, UnresolvedBrilligCall};
use acvm::PartialWitnessGenerator;
Expand Down Expand Up @@ -32,23 +31,21 @@ pub fn execute_circuit(
// Execute foreign calls
// TODO(#1615): "oracle_print_impl" and "oracle_print_array_impl" are just identity funcs
if foreign_call_wait_info.function == "oracle_print_impl" {
let values = &foreign_call_wait_info.inputs[0];
println!("{:?}", values[0].to_field().to_hex());
brillig.foreign_call_results.push(ForeignCallResult {
values: vec![vec![foreign_call_wait_info.inputs[0][0]]],
});
let value = foreign_call_wait_info.inputs[0][0];
println!("{:?}", value.to_field().to_hex());
brillig.foreign_call_results.push(value.into());
} else if foreign_call_wait_info.function == "oracle_print_array_impl" {
let mut outputs_hex = Vec::new();
for value in foreign_call_wait_info.inputs.clone() {
outputs_hex.push(value[0].to_field().to_hex());
for values in foreign_call_wait_info.inputs.clone() {
for value in values {
outputs_hex.push(value.to_field().to_hex());
}
}
// Join all of the hex strings using a comma
let comma_separated_elements = outputs_hex.join(", ");
let output_witnesses_string = "[".to_owned() + &comma_separated_elements + "]";
println!("{output_witnesses_string}");
brillig.foreign_call_results.push(ForeignCallResult {
values: vec![vec![foreign_call_wait_info.inputs[0][0]]],
});
brillig.foreign_call_results.push(foreign_call_wait_info.inputs[0][0].into());
}

let mut next_opcodes_for_solving = vec![Opcode::Brillig(brillig)];
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ use crate::ssa_refactor::ir::{
types::{NumericType, Type},
value::{Value, ValueId},
};
use acvm::acir::brillig_vm::{BinaryFieldOp, BinaryIntOp, RegisterIndex, RegisterValueOrArray};
use acvm::acir::brillig_vm::{BinaryFieldOp, BinaryIntOp, RegisterIndex, RegisterOrMemory};
use acvm::FieldElement;
use iter_extended::vecmap;

Expand Down Expand Up @@ -387,12 +387,12 @@ impl<'block> BrilligBlock<'block> {
&mut self,
value_id: ValueId,
dfg: &DataFlowGraph,
) -> RegisterValueOrArray {
) -> RegisterOrMemory {
let register_index = self.convert_ssa_value(value_id, dfg);
let typ = dfg[value_id].get_type();
match typ {
Type::Numeric(_) => RegisterValueOrArray::RegisterIndex(register_index),
Type::Array(_, size) => RegisterValueOrArray::HeapArray(register_index, size),
Type::Numeric(_) => RegisterOrMemory::RegisterIndex(register_index),
Type::Array(_, size) => RegisterOrMemory::HeapArray(register_index, size),
_ => {
unreachable!("type not supported for conversion into brillig register")
}
Expand Down
7 changes: 3 additions & 4 deletions crates/noirc_evaluator/src/brillig/brillig_ir.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,7 @@ use self::{
};
use acvm::{
acir::brillig_vm::{
BinaryFieldOp, BinaryIntOp, Opcode as BrilligOpcode, RegisterIndex, RegisterValueOrArray,
Value,
BinaryFieldOp, BinaryIntOp, Opcode as BrilligOpcode, RegisterIndex, RegisterOrMemory, Value,
},
FieldElement,
};
Expand Down Expand Up @@ -419,8 +418,8 @@ impl BrilligContext {
pub(crate) fn foreign_call_instruction(
&mut self,
func_name: String,
inputs: &[RegisterValueOrArray],
outputs: &[RegisterValueOrArray],
inputs: &[RegisterOrMemory],
outputs: &[RegisterOrMemory],
) {
debug_show::foreign_call_instruction(func_name.clone(), inputs, outputs);
// TODO(https://github.com/noir-lang/acvm/issues/366): Enable multiple inputs and outputs to a foreign call
Expand Down
21 changes: 13 additions & 8 deletions crates/noirc_evaluator/src/brillig/brillig_ir/debug_show.rs
Original file line number Diff line number Diff line change
@@ -1,9 +1,7 @@
///! This module contains functions for producing a higher level view disassembler of Brillig.
use super::BrilligBinaryOp;
use crate::brillig::brillig_ir::{ReservedRegisters, BRILLIG_MEMORY_ADDRESSING_BIT_SIZE};
use acvm::acir::brillig_vm::{
BinaryFieldOp, BinaryIntOp, RegisterIndex, RegisterValueOrArray, Value,
};
use acvm::acir::brillig_vm::{BinaryFieldOp, BinaryIntOp, RegisterIndex, RegisterOrMemory, Value};

/// Controls whether debug traces are enabled
const ENABLE_DEBUG_TRACE: bool = true;
Expand Down Expand Up @@ -98,13 +96,20 @@ impl DebugToString for Value {
}
}

impl DebugToString for RegisterValueOrArray {
impl DebugToString for RegisterOrMemory {
fn debug_to_string(&self) -> String {
match self {
RegisterValueOrArray::RegisterIndex(index) => index.debug_to_string(),
RegisterValueOrArray::HeapArray(index, size) => {
RegisterOrMemory::RegisterIndex(index) => index.debug_to_string(),
RegisterOrMemory::HeapArray(index, size) => {
format!("{}[0..{}]", index.debug_to_string(), size)
}
RegisterOrMemory::HeapVector(location_index, length_index) => {
format!(
"{}[0..{}]",
location_index.debug_to_string(),
length_index.debug_to_string()
)
}
}
}
}
Expand Down Expand Up @@ -173,8 +178,8 @@ pub(crate) fn not_instruction(condition: RegisterIndex, result: RegisterIndex) {
/// Processes a foreign call instruction.
pub(crate) fn foreign_call_instruction(
func_name: String,
inputs: &[RegisterValueOrArray],
outputs: &[RegisterValueOrArray],
inputs: &[RegisterOrMemory],
outputs: &[RegisterOrMemory],
) {
debug_println!(" FOREIGN_CALL {} ({}) => {}", func_name, inputs, outputs);
}
Expand Down