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Make types in SSA binary operations match #4275
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This was referenced Feb 6, 2024
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# Description ## Problem\* Partial work towards #4275 ## Summary\* ## Additional Context ## Documentation\* Check one: - [x] No documentation needed. - [ ] Documentation included in this PR. - [ ] **[Exceptional Case]** Documentation to be submitted in a separate PR. # PR Checklist\* - [ ] I have tested the changes locally. - [x] I have formatted the changes with [Prettier](https://prettier.io/) and/or `cargo fmt` on default settings.
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# Description ## Problem\* Partial work towards #4275 ## Summary\* We were mixing Field and u64 types when accessing arrays. Since we index arrays by u64s, always cast array/slice addressing values to u64. ## Additional Context ## Documentation\* Check one: - [x] No documentation needed. - [ ] Documentation included in this PR. - [ ] **[Exceptional Case]** Documentation to be submitted in a separate PR. # PR Checklist\* - [x] I have tested the changes locally. - [x] I have formatted the changes with [Prettier](https://prettier.io/) and/or `cargo fmt` on default settings.
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# Description ## Problem\* Partial work towards #4275 ## Summary\* Also use the array index type (u64) for assign_lvalue_index. ## Additional Context ## Documentation\* Check one: - [x] No documentation needed. - [ ] Documentation included in this PR. - [ ] **[Exceptional Case]** Documentation to be submitted in a separate PR. # PR Checklist\* - [x] I have tested the changes locally. - [x] I have formatted the changes with [Prettier](https://prettier.io/) and/or `cargo fmt` on default settings.
This was referenced Feb 7, 2024
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# Description ## Problem\* Partial work towards #4275 ## Summary\* Previously, SSA was issuing (lhs_type, Field) DIV for right shifts. However this is wrong if we support shifts by the bit size (`u1 >> 1`) This is interpreted in acir_gen as an euclidean division with bit_size = lhs_type.bit_size(). However, u1 >> 1 worked because of a + 1 that is in euclidean division https://github.com/noir-lang/noir/blob/0e073037b00212fd17fc8ca9c531b567614eb4c5/compiler/noirc_evaluator/src/ssa/acir_gen/acir_ir/acir_variable.rs#L703 (and it failed in unconstrained functions since they don't codegen that extraneous + 1) ## Additional Context ## Documentation\* Check one: - [x] No documentation needed. - [ ] Documentation included in this PR. - [ ] **[Exceptional Case]** Documentation to be submitted in a separate PR. # PR Checklist\* - [x] I have tested the changes locally. - [x] I have formatted the changes with [Prettier](https://prettier.io/) and/or `cargo fmt` on default settings. --------- Co-authored-by: TomAFrench <[email protected]>
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# Description ## Problem\* Partial work towards #4275 ## Summary\* ## Additional Context Tested in aztec-packages here AztecProtocol/aztec-packages#4556 ## Documentation\* Check one: - [x] No documentation needed. - [ ] Documentation included in this PR. - [ ] **[Exceptional Case]** Documentation to be submitted in a separate PR. # PR Checklist\* - [x] I have tested the changes locally. - [x] I have formatted the changes with [Prettier](https://prettier.io/) and/or `cargo fmt` on default settings.
This was referenced Feb 15, 2024
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# Description ## Problem\* Resolves #4275 ## Summary\* Adds a check in insert_binary to make sure we don't start codegening non-matching binary ops again. ## Additional Context ## Documentation\* Check one: - [x] No documentation needed. - [ ] Documentation included in this PR. - [ ] **[Exceptional Case]** Documentation to be submitted in a separate PR. # PR Checklist\* - [x] I have tested the changes locally. - [x] I have formatted the changes with [Prettier](https://prettier.io/) and/or `cargo fmt` on default settings.
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Problem
Upcoming changes in brillig will require that the types of both operands in binary operations match. Even though in noir we enforce matching types, we don't in SSA, and the SSA codegen sometimes issues binary operations where the types of LHS and RHS don't match.
Happy Case
This assertion shouldn't fail in tests:
Alternatives Considered
We could upcast in the codegen as we do now. But brillig for the AVM won't support euclidean divisions of field types, so this would still be an issue. Also, it makes sense for SSA to respect this binary operation rule as noir does, and it would simplify codegens after SSA.
Additional Context
Current cases where this check is blowing up
Initial tests failing with this check:
Current tests failing with this check:
Would you like to submit a PR for this Issue?
No
Support Needs
No response
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