deps: V8: backport 77599ffe0a74

Original commit message: [riscv64] Add block before LoadAddress fix node.js DCHECK failed issue: riscv-collab/v8#514 Change-Id: I07f40e6aca05be3eb7304a43235185fd40ebc1f2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3260979 Reviewed-by: ji qiu <[email protected]> Commit-Queue: ji qiu <[email protected]> Auto-Submit: Yahan Lu <[email protected]> Cr-Commit-Position: refs/heads/main@{#77750} Refs: v8/v8@77599ffe0a74
nodejs · Jan 17, 2022 · f18bb63 · f18bb63
1 parent 81e50d8
commit f18bb63
Show file tree

Hide file tree

Showing 3 changed files with 3 additions and 1 deletion.
diff --git a/common.gypi b/common.gypi
@@ -36,7 +36,7 @@
 
     # Reset this number to 0 on major V8 upgrades.
     # Increment by one for each non-official patch applied to deps/v8.
-    'v8_embedder_string': '-node.18',
+    'v8_embedder_string': '-node.19',
 
     ##### V8 defaults for Node.js #####
 

diff --git a/deps/v8/src/baseline/riscv64/baseline-assembler-riscv64-inl.h b/deps/v8/src/baseline/riscv64/baseline-assembler-riscv64-inl.h
@@ -438,6 +438,7 @@ void BaselineAssembler::Switch(Register reg, int case_value_base,
   DCHECK(is_int32(imm64));
   int32_t Hi20 = (((int32_t)imm64 + 0x800) >> 12);
   int32_t Lo12 = (int32_t)imm64 << 20 >> 20;
+  __ BlockTrampolinePoolFor(2);
   __ auipc(temp, Hi20);  // Read PC + Hi20 into t6
   __ addi(temp, temp, Lo12);  // jump PC + Hi20 + Lo12
 

diff --git a/deps/v8/src/codegen/riscv64/macro-assembler-riscv64.cc b/deps/v8/src/codegen/riscv64/macro-assembler-riscv64.cc
@@ -3485,6 +3485,7 @@ void TurboAssembler::LoadAddress(Register dst, Label* target,
   if (CalculateOffset(target, &offset, OffsetSize::kOffset32)) {
     int32_t Hi20 = (((int32_t)offset + 0x800) >> 12);
     int32_t Lo12 = (int32_t)offset << 20 >> 20;
+    BlockTrampolinePoolScope block_trampoline_pool(this);
     auipc(dst, Hi20);
     addi(dst, dst, Lo12);
   } else {