Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

update dmidecode.c to smibios 3.3 (7.1-7.14) #32

Closed
wants to merge 37 commits into from

Conversation

HuO50
Copy link
Collaborator

@HuO50 HuO50 commented May 11, 2022

Hello , All
I update dmidecode.c to smibios version 3.3.
this pr include smibios 7.1-7.14, about bios info, processor(processor and processor related), cache, system slot, bios language;
please review and comments

ref: DSP0134_3.3 

joshuazzhu added 12 commits May 10, 2022 11:12
1. add TPM Device to types[];
2. adjust boundary of code, add code >= 128
for OEM specific scenario;
1. add dmi_bios_rom_size function for
higher units: MB, GB;
2. remove origin units KB;
1. add dmi_chassis_type 7 classes, from 'Tablet'
to 'Stick PC';
2. modify available boardary;
1. add processor family2[] list
1. update dmi_processor_id type;
2. update AMD judgement boardary;
1. add upgrade[] from 0x2D to 0x3C; modify boundary to 0x3C
1. add dmi_memory_module_error status[] & add "error status" attribute
1. modify dmi_cache_size & add dmi_cache_size_2 for
Maximumsize and InstalledSize
2. add dmi_cache_size_2 and use dmi_add_memory_size
for large cache size
1. update dmi_port_connector_type, add type[] to 0x23
and code boundary
1. add data bus width attribute.
2. add dmi_slot_peers function to for peer devices.
3. add dmi_slot_segment_bus_func for bus address.
4. update dmi_slot_type type[], add type_0x30 for CXL Flexbus, add
PCI Express 4, also modify judgement boundary.
5. update 'Unavailable' to dmi_slot_current_usage usages[].
6. update dmi_slot_length length[] 2.5/3.5 drive form factor.
7. update dmi_slot_id case 0xB1:0xBD for PCI express
1. add language description format for abbreviated or long mode.
2. add currently installed language attribute
@lian-bo
Copy link
Collaborator

lian-bo commented May 13, 2022

Thank you for the patchset, Zhongze Hu.
As we discussed offline, could you please do extra work for updating to SMBIO3.3 and later? Once everything looks good or patchset is ready, I will push the new patchset to github. What do you think?

joshuazzhu and others added 8 commits August 30, 2022 20:33
1. add upgrade[] from 0x2D to 0x3C; modify boundary to 0x3C
1. add dmi_memory_module_error status[] & add "error status" attribute
1. modify dmi_cache_size & add dmi_cache_size_2 for
Maximumsize and InstalledSize
2. add dmi_cache_size_2 and use dmi_add_memory_size
for large cache size
1. update dmi_port_connector_type, add type[] to 0x23
and code boundary
1. add data bus width attribute.
2. add dmi_slot_peers function to for peer devices.
3. add dmi_slot_segment_bus_func for bus address.
4. update dmi_slot_type type[], add type_0x30 for CXL Flexbus, add
PCI Express 4, also modify judgement boundary.
5. update 'Unavailable' to dmi_slot_current_usage usages[].
6. update dmi_slot_length length[] 2.5/3.5 drive form factor.
7. update dmi_slot_id case 0xB1:0xBD for PCI express
1. add language description format for abbreviated or long mode.
2. add currently installed language attribute
2. Add OUT_OF_SPEC macro instead of "outofspec"
@lian-bo
Copy link
Collaborator

lian-bo commented Oct 26, 2022

We can close this PR32 because another PR( #46) has been merged. Thanks.

@lian-bo lian-bo closed this Oct 26, 2022
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants