UVVM AXI BFM fatal error

[erick166]

I am getting the following error while running a testcase with the AXI BFM from UVVM:

fatal: (init): cannot handle value kind 4 in lvn_value_num
[00007FF60DBA6EE0]
[00007FF60DC51406]
[00007FF60DBA5E73]
[00007FF60DD2E771] vhpi_is_printable+0x94541
[00007FF60DD2E354] vhpi_is_printable+0x94124
[00007FF60DD117D1] vhpi_is_printable+0x775a1
[00007FF60DD2B2B0] vhpi_is_printable+0x91080
[00007FF60DC82469] std_env_get_assert_format+0x7739
[00007FF60DC6B8C8] nvc_current_delta+0x2838
[00007FF60DC6B7CB] nvc_current_delta+0x273b
[00007FF60DC6AED5] nvc_current_delta+0x1e45
[00007FF60DBA0140]
[00007FF60DB9E257]
[00007FF60DB98D48]
[00007FF60CB4D9B5]
[00007FF60CB4DA06]
[00007FF90A99257D] BaseThreadInitThunk+0x1d
[00007FF90BD2AF28] RtlUserThreadStart+0x28
Please report this bug at https://github.com/nickg/nvc/issues
Error: Program ended with exit code 1

I've tried removing most of the extra code from the testcase:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library uvvm_util;
context uvvm_util.uvvm_util_context;

library bitvis_vip_axi;
use bitvis_vip_axi.axi_bfm_pkg.all;

entity axi_bfm_tb is
end entity axi_bfm_tb;

architecture tb of axi_bfm_tb is

  constant C_CLK_PERIOD : time   := 10 ns;

  signal clk    : std_logic := '0';
  signal axi_if : t_axi_if(write_address_channel(awid(8 - 1 downto 0),
                                                 awaddr(32 - 1 downto 0),
                                                 awuser(8 - 1 downto 0)),
                           write_data_channel(wdata(32 - 1 downto 0),
                                              wstrb(4 - 1 downto 0),
                                              wuser(8 - 1 downto 0)),
                           write_response_channel(bid(8 - 1 downto 0),
                                                  buser(8 - 1 downto 0)),
                           read_address_channel(arid(8 - 1 downto 0),
                                                araddr(32 - 1 downto 0),
                                                aruser(8 - 1 downto 0)),
                           read_data_channel(rid(8 - 1 downto 0),
                                             rdata(32 - 1 downto 0),
                                             ruser(8 - 1 downto 0)));

begin

  clock_generator(clk, C_CLK_PERIOD);

  p_main : process
    variable axi_bfm_config       : t_axi_bfm_config                   := C_AXI_BFM_CONFIG_DEFAULT;
    variable v_buser_value        : std_logic_vector(7 downto 0);
    variable v_bresp_value        : t_xresp;
  begin
    axi_bfm_config.clock_period       := C_CLK_PERIOD;
    axi_bfm_config.num_aw_pipe_stages := 0;
    axi_bfm_config.num_w_pipe_stages  := 0;
    axi_bfm_config.num_b_pipe_stages  := 0;
    axi_bfm_config.num_ar_pipe_stages := 0;
    axi_bfm_config.num_r_pipe_stages  := 0;
    axi_if                            <= init_axi_if_signals(32, 32, 8, 8);

    wait for C_CLK_PERIOD;

    axi_write(awaddr_value  => x"00000004",
              wdata_value   => t_slv_array'(x"12345678", x"33333333"),
              buser_value   => v_buser_value,
              bresp_value   => v_bresp_value,
              msg           => "Testing axi write",
              clk           => clk,
              axi_if        => axi_if);

    report_alert_counters(FINAL);
    log(ID_LOG_HDR, "SIMULATION COMPLETED");
    std.env.stop;
    wait;
  end process;
end architecture;