nvc crashes with generic package passed to generic map in entity instantiation

[johonkanen]

When a package is given to an entity through generic map with generic types, nvc crashes

--------------------------------------------------
package test_generic_pkg is
    generic(type              g_countertype ;
            g_initval :       g_countertype ;
            function "+" (l : g_countertype ; r : integer) return g_countertype );

    subtype countertype is g_countertype;
    constant init_counter : g_countertype := g_initval;

end package test_generic_pkg;

--------------------------------------------------
LIBRARY ieee  ; 
    USE ieee.NUMERIC_STD.all  ; 
    USE ieee.std_logic_1164.all  ; 

entity gentest is
    generic(package test_pkg is new work.test_generic_pkg generic map(<>));
    port (
        clk : in std_logic
    );
end entity gentest;

architecture test of gentest is

    use test_pkg.all;
    signal counter : countertype := init_counter;

begin
    process(clk)
    begin
        if rising_edge(clk) then
            counter <= counter + 1;
        end if;
    end process;

end test;
--------------------------------------------------
LIBRARY ieee  ; 
    USE ieee.NUMERIC_STD.all  ; 
    USE ieee.std_logic_1164.all  ; 

entity gen_package_tb is
end;

architecture vunit_simulation of gen_package_tb is

    subtype sig is signed(15 downto 0);
    package test_pkg is new work.test_generic_pkg generic map(g_countertype => sig, g_initval => to_signed(-6, 16), "+" => "+");
    use test_pkg.all;

    constant clock_period      : time    := 1 ns;
    constant simtime_in_clocks : integer := 50;
    
    signal simulator_clock     : std_logic := '0';
    signal simulation_counter  : natural   := 0;
    -----------------------------------
    -- simulation specific signals ----
    signal counter : countertype := init_counter;

begin

------------------------------------------------------------------------
    simtime : process
    begin
        wait for simtime_in_clocks*clock_period;
        assert false report "Simulation Finished" severity failure;
    end process simtime;	

    simulator_clock <= not simulator_clock after clock_period/2.0;
------------------------------------------------------------------------

    stimulus : process(simulator_clock)

    begin
        if rising_edge(simulator_clock) then
            simulation_counter <= simulation_counter + 1;
            counter <= counter + 1;
            assert counter = init_counter + simulation_counter report "generic package did not work correctly" severity failure;

        end if; -- rising_edge
    end process stimulus;	
------------------------------------------------------------------------
u_gentest : entity work.gentest
generic map(test_pkg)
port map(simulator_clock);

end vunit_simulation;

example run
$ /c/Program\ files/NVC/bin/nvc.exe -a testbenches/gen_package_tb.vhd -e gen_package_tb -r
** Fatal: tree kind T_GENERIC_DECL does not have item I_IDENT2

C:\dev\tube_amplifier_power_supply\testbenches\gen_package_tb.vhd:5
|
5 | function "+" (l : g_countertype ; r : integer) return g_countertype );
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[00007FF697515DC0]
[00007FF69760E0E7] vhpi_is_printable+0x3c37
[00007FF69759F821]
[00007FF697589CED]
[00007FF69758CF2E]
[00007FF69758ED63]
[00007FF69759004A]
[00007FF697586350]
[00007FF69756C4F4]
[00007FF69756820D]
[00007FF69756C359]
[00007FF69756820D]
[00007FF6975664CF]
[00007FF69750CF94]
[00007FF69750E39A]
[00007FF697507AFB]
[00007FF696332CB1]
[00007FF696332D06]
[00007FFD5565257D] BaseThreadInitThunk+0x1d
[00007FFD5604AF28] RtlUserThreadStart+0x28

Please report this bug at https://github.com/nickg/nvc/issues

[johonkanen]

commeting out the entity instantiation makes the tb run through to the "simulation finished" - report

/*
u_gentest : entity work.gentest
generic map(test_pkg)
port map(simulator_clock);
*/

$ /c/Program\ files/NVC/bin/nvc.exe -a testbenches/gen_package_tb.vhd -e gen_package_tb -r
** Failure: 50ns+0: Simulation Finished
   Process :gen_package_tb:simtime at C:\dev\tube_amplifier_power_supply\testbenches\gen_package_tb.vhd:64