Unconstrained conversions causing segfault

[avelure]

This MWE is from here
https://github.com/ghdl/ghdl/tree/master/testsuite/gna/ticket97
https://sourceforge.net/p/ghdl-updates/tickets/97/

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity foo is end entity;
architecture arch of foo is
begin
  process is
    procedure xyzzy( v : inout unsigned ) is
    begin
      v := v + 1;
    end procedure;

    variable x : std_ulogic_vector( 7 downto 0 );
  begin
    -- trying to do an inout conversion triggers the bug:
    xyzzy( std_ulogic_vector( v ) => unsigned( x ) );
    wait;
  end process;
end architecture;

$ nvc --std=08 --messages=compact -a --psl 6e4126f178464d32a6f13c49c56d2bf3ea6bb7c7f4b9ef03a2aedddcc7694bc5

*** Caught exception c0000005 (EXCEPTION_ACCESS_VIOLATION) [address=0000000000000000, ip=00007FF62534741D] ***

[00007FF625233140]
[00007FF6252334F9]
[00007FFAA11AD553] UnhandledExceptionFilter+0x1f3
[00007FFAA3C0868A] strncpy+0x2cba
[00007FFAA3BC3E63] _C_specific_handler+0x93
[00007FFAA3C03D6F] _chkstk+0x9f
[00007FFAA3ABF358] RtlWow64GetCurrentCpuArea+0xa98
[00007FFAA3C036AE] KiUserExceptionDispatcher+0x2e
[00007FF62534741D] vhpi_is_printable+0x2615d
[00007FF625342AFB] vhpi_is_printable+0x2183b
[00007FF6252604B0]
[00007FF62527700D]
[00007FF62523B5F2]
[00007FF625239A1A]
[00007FF625236046]
[00007FF62529D0D0]
[00007FF625223701]
[00007FF62522290B]
[00007FF625211313]
[00007FF625211366]
[00007FFAA221DBE7] BaseThreadInitThunk+0x17
[00007FFAA3B25A4C] RtlUserThreadStart+0x2c

nvc 1.14.0 (1.14.0.r7.g4cb3822b) (Using LLVM 18.1.8) [x86_64-w64-mingw32]

Please report this bug at https://github.com/nickg/nvc/issues

Segmentation fault

$ /opt/ghdl_mcode/bin/ghdl -a --std=08 -fpsl 6e4126f178464d32a6f13c49c56d2bf3ea6bb7c7f4b9ef03a2aedddcc7694bc5
6e4126f178464d32a6f13c49c56d2bf3ea6bb7c7f4b9ef03a2aedddcc7694bc5:16:46:error: type of actual conversion must be fully constrained
    xyzzy( std_ulogic_vector( v ) => unsigned( x ) );
                                             ^
6e4126f178464d32a6f13c49c56d2bf3ea6bb7c7f4b9ef03a2aedddcc7694bc5:16:29:error: type of formal conversion must be fully constrained
    xyzzy( std_ulogic_vector( v ) => unsigned( x ) );
                            ^