remove tabs (apache#3603)

neo-ai · Sep 6, 2019 · fc527e3 · fc527e3
1 parent 27f6962
commit fc527e3
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Showing 10 changed files with 85 additions and 85 deletions.
diff --git a/vta/hardware/chisel/src/main/scala/core/Compute.scala b/vta/hardware/chisel/src/main/scala/core/Compute.scala
@@ -64,9 +64,9 @@ class Compute(debug: Boolean = false)(implicit p: Parameters) extends Module {
 
   val inst_type = Cat(dec.io.isFinish,
                       dec.io.isAlu,
-		      dec.io.isGemm,
-		      dec.io.isLoadAcc,
-		      dec.io.isLoadUop).asUInt
+                      dec.io.isGemm,
+                      dec.io.isLoadAcc,
+                      dec.io.isLoadUop).asUInt
 
   val sprev = inst_q.io.deq.valid & Mux(dec.io.pop_prev, s(0).io.sready, true.B)
   val snext = inst_q.io.deq.valid & Mux(dec.io.pop_next, s(1).io.sready, true.B)
@@ -87,11 +87,11 @@ class Compute(debug: Boolean = false)(implicit p: Parameters) extends Module {
   switch (state) {
     is (sIdle) {
       when (start) {
-	when (dec.io.isSync) {
+        when (dec.io.isSync) {
           state := sSync
-	} .elsewhen (inst_type.orR) {
+        } .elsewhen (inst_type.orR) {
           state := sExe
-	}
+        }
       }
     }
     is (sSync) {

diff --git a/vta/hardware/chisel/src/main/scala/core/Fetch.scala b/vta/hardware/chisel/src/main/scala/core/Fetch.scala
@@ -77,15 +77,15 @@ class Fetch(debug: Boolean = false)(implicit p: Parameters) extends Module {
     is (sIdle) {
       when (pulse) {
         state := sReadCmd
-	when (xsize < xmax) {
+        when (xsize < xmax) {
           rlen := xsize
-	  ilen := xsize >> 1.U
+          ilen := xsize >> 1.U
           xrem := 0.U
-	} .otherwise {
+        } .otherwise {
           rlen := xmax - 1.U
-	  ilen := (xmax >> 1.U) - 1.U
+          ilen := (xmax >> 1.U) - 1.U
           xrem := xsize - xmax
-	}
+        }
       }
     }
     is (sReadCmd) {
@@ -104,7 +104,7 @@ class Fetch(debug: Boolean = false)(implicit p: Parameters) extends Module {
           state := sDrain
         } .otherwise {
           state := sReadLSB
-	}
+        }
       }
     }
     is (sDrain) {
@@ -114,12 +114,12 @@ class Fetch(debug: Boolean = false)(implicit p: Parameters) extends Module {
         } .elsewhen (xrem < xmax) {
           state := sReadCmd
           rlen := xrem
-	  ilen := xrem >> 1.U
+          ilen := xrem >> 1.U
           xrem := 0.U
         } .otherwise {
           state := sReadCmd
           rlen := xmax - 1.U
-	  ilen := (xmax >> 1.U) - 1.U
+          ilen := (xmax >> 1.U) - 1.U
           xrem := xrem - xmax
         }
       }

diff --git a/vta/hardware/chisel/src/main/scala/core/Load.scala b/vta/hardware/chisel/src/main/scala/core/Load.scala
@@ -65,9 +65,9 @@ class Load(debug: Boolean = false)(implicit p: Parameters) extends Module {
       when (start) {
         when (dec.io.isSync) {
           state := sSync
-	} .elsewhen (dec.io.isInput || dec.io.isWeight) {
+        } .elsewhen (dec.io.isInput || dec.io.isWeight) {
           state := sExe
-	}
+        }
       }
     }
     is (sSync) {
@@ -121,10 +121,10 @@ class Load(debug: Boolean = false)(implicit p: Parameters) extends Module {
     when (state === sExe) {
       when (done) {
         when (dec.io.isInput) {
-	  printf("[Load] done input\n")
-	} .elsewhen (dec.io.isWeight) {
-	  printf("[Load] done weight\n")
-	}
+          printf("[Load] done input\n")
+        } .elsewhen (dec.io.isWeight) {
+          printf("[Load] done weight\n")
+        }
       }
     }
   }

diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala
@@ -91,13 +91,13 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
     is (sIdle) {
       when (io.start) {
         state := sReadCmd
-	when (xsize < xmax) {
+        when (xsize < xmax) {
           xlen := xsize
           xrem := 0.U
-	} .otherwise {
+        } .otherwise {
           xlen := xmax - 1.U
           xrem := xsize - xmax
-	}
+        }
       }
     }
     is (sReadCmd) {

diff --git a/vta/hardware/chisel/src/main/scala/core/Store.scala b/vta/hardware/chisel/src/main/scala/core/Store.scala
@@ -60,9 +60,9 @@ class Store(debug: Boolean = false)(implicit p: Parameters) extends Module {
       when (start) {
         when (dec.io.isSync) {
           state := sSync
-	} .elsewhen (dec.io.isStore) {
+        } .elsewhen (dec.io.isStore) {
           state := sExe
-	}
+        }
       }
     }
     is (sSync) {
@@ -107,7 +107,7 @@ class Store(debug: Boolean = false)(implicit p: Parameters) extends Module {
     }
     when (state === sExe) {
       when (done) {
-	printf("[Store] done\n")
+        printf("[Store] done\n")
       }
     }
   }

diff --git a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
@@ -43,7 +43,7 @@ class Alu(implicit p: Parameters) extends Module {
                 Mux(io.a < io.b, io.b, io.a),
                 io.a + io.b,
                 io.a >> n,
-	        io.a << m)
+                io.a << m)
 
   val opmux = Seq.tabulate(ALU_OP_NUM)(i => ALU_OP(i) -> fop(i))
   io.y := MuxLookup(io.opcode, io.a, opmux)
@@ -157,8 +157,8 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
     is (sExe) {
       when (alu.io.out.data.valid) {
         when ((cnt_o === dec.lp_0 - 1.U) &&
-	      (cnt_i === dec.lp_1 - 1.U) &&
-	      (uop_idx === uop_end - 1.U)) {
+              (cnt_i === dec.lp_1 - 1.U) &&
+              (uop_idx === uop_end - 1.U)) {
           state := sIdle
         } .otherwise {
           state := sReadUop
@@ -169,8 +169,8 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
 
   when (state === sIdle ||
          (state === sExe &&
-	  alu.io.out.data.valid &&
-	  uop_idx === uop_end - 1.U)) {
+          alu.io.out.data.valid &&
+          uop_idx === uop_end - 1.U)) {
     uop_idx := dec.uop_begin
   } .elsewhen (state === sExe && alu.io.out.data.valid) {
     uop_idx := uop_idx + 1.U
@@ -183,7 +183,7 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
   } .elsewhen (state === sExe &&
                alu.io.out.data.valid &&
                uop_idx === uop_end - 1.U &&
-	       cnt_i === dec.lp_1 - 1.U) {
+               cnt_i === dec.lp_1 - 1.U) {
     cnt_o := cnt_o + 1.U
     dst_o := dst_o + dec.dst_0
     src_o := src_o + dec.src_0
@@ -199,7 +199,7 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
     src_i := src_o
   } .elsewhen (state === sExe &&
                alu.io.out.data.valid &&
-	       uop_idx === uop_end - 1.U) {
+               uop_idx === uop_end - 1.U) {
     cnt_i := cnt_i + 1.U
     dst_i := dst_i + dec.dst_1
     src_i := src_i + dec.src_1

diff --git a/vta/hardware/chisel/src/main/scala/core/TensorGemm.scala b/vta/hardware/chisel/src/main/scala/core/TensorGemm.scala
@@ -180,10 +180,10 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
   val done = inflight === 0.U &
              ((state === sExe &
               cnt_o === dec.lp_0 - 1.U &
-	      cnt_i === dec.lp_1 - 1.U &
-	      uop_idx === uop_end - 1.U &
-	      inflight === 0.U) |
-	     state === sWait)
+              cnt_i === dec.lp_1 - 1.U &
+              uop_idx === uop_end - 1.U &
+              inflight === 0.U) |
+             state === sWait)
 
   switch (state) {
     is (sIdle) {
@@ -204,11 +204,11 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
       when ((cnt_o === dec.lp_0 - 1.U) &&
             (cnt_i === dec.lp_1 - 1.U) &&
             (uop_idx === uop_end - 1.U)) {
-	when (inflight =/= 0.U) {
+        when (inflight =/= 0.U) {
           state := sWait
-	} .otherwise {
+        } .otherwise {
           state := sIdle
-	}
+        }
       } .otherwise {
         state := sReadUop
       }
@@ -232,7 +232,7 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
 
   when (state === sIdle ||
          (state === sExe &&
-	  uop_idx === uop_end - 1.U)) {
+          uop_idx === uop_end - 1.U)) {
     uop_idx := dec.uop_begin
   } .elsewhen (state === sExe) {
     uop_idx := uop_idx + 1.U
@@ -244,8 +244,8 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
     inp_o := 0.U
     wgt_o := 0.U
   } .elsewhen (state === sExe &&
-	       uop_idx === uop_end - 1.U &&
-	       cnt_i === dec.lp_1 - 1.U) {
+               uop_idx === uop_end - 1.U &&
+               cnt_i === dec.lp_1 - 1.U) {
     cnt_o := cnt_o + 1.U
     acc_o := acc_o + dec.acc_0
     inp_o := inp_o + dec.inp_0
@@ -263,7 +263,7 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
     inp_i := inp_o
     wgt_i := wgt_o
   } .elsewhen (state === sExe &&
-	       uop_idx === uop_end - 1.U) {
+               uop_idx === uop_end - 1.U) {
     cnt_i := cnt_i + 1.U
     acc_i := acc_i + dec.acc_1
     inp_i := inp_i + dec.inp_1

diff --git a/vta/hardware/chisel/src/main/scala/core/TensorLoad.scala b/vta/hardware/chisel/src/main/scala/core/TensorLoad.scala
@@ -67,20 +67,20 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)
       when (io.start) {
         when (dec.ypad_0 =/= 0.U) {
           state := sYPad0
-	} .elsewhen (dec.xpad_0 =/= 0.U) {
+        } .elsewhen (dec.xpad_0 =/= 0.U) {
           state := sXPad0
-	} .otherwise {
+        } .otherwise {
           state := sReadCmd
-	}
+        }
       }
     }
     is (sYPad0) {
       when (yPadCtrl0.io.done) {
         when (dec.xpad_0 =/= 0.U) {
           state := sXPad0
-	} .otherwise {
+        } .otherwise {
           state := sReadCmd
-	}
+        }
       }
     }
     is (sXPad0) {
@@ -96,22 +96,22 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)
     is (sReadData) {
       when (io.vme_rd.data.valid) {
         when (dataCtrl.io.done) {
-	  when (dec.xpad_1 =/= 0.U) {
-	    state := sXPad1
-	  } .elsewhen (dec.ypad_1 =/= 0.U) {
-	    state := sYPad1
-	  } .otherwise  {
-	    state := sIdle
-	  }
-	} .elsewhen (dataCtrl.io.stride || dataCtrl.io.split) {
           when (dec.xpad_1 =/= 0.U) {
-	    state := sXPad1
-	  } .elsewhen (dec.xpad_0 =/= 0.U) {
+            state := sXPad1
+          } .elsewhen (dec.ypad_1 =/= 0.U) {
+            state := sYPad1
+          } .otherwise  {
+            state := sIdle
+          }
+        } .elsewhen (dataCtrl.io.stride || dataCtrl.io.split) {
+          when (dec.xpad_1 =/= 0.U) {
+            state := sXPad1
+          } .elsewhen (dec.xpad_0 =/= 0.U) {
             state := sXPad0
-	  } .otherwise {
+          } .otherwise {
               state := sReadCmd
-	  }
-	}
+          }
+        }
       }
     }
     is (sXPad1) {
@@ -161,9 +161,9 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)
 
   xPadCtrl0.io.start := dec.xpad_0 =/= 0.U &
                           ((state === sIdle & io.start) |
-			  (state === sYPad0 & yPadCtrl0.io.done) |
+                          (state === sYPad0 & yPadCtrl0.io.done) |
                           (io.vme_rd.data.fire() & ~dataCtrlDone & (dataCtrl.io.stride | dataCtrl.io.split) & dec.xpad_1 === 0.U) |
-			  (state === sXPad1 & xPadCtrl1.io.done & ~dataCtrlDone))
+                          (state === sXPad1 & xPadCtrl1.io.done & ~dataCtrlDone))
 
   xPadCtrl1.io.start := dec.xpad_1 =/= 0.U & io.vme_rd.data.fire() &
                           ((dataCtrl.io.done) |
@@ -184,8 +184,8 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)
   // write-to-sram
   val isZeroPad = state === sYPad0 |
                   state === sXPad0 |
-		  state === sXPad1 |
-		  state === sYPad1
+                  state === sXPad1 |
+                  state === sYPad1
 
   when (state === sIdle || state === sReadCmd || tag === (tp.numMemBlock - 1).U) {
     tag := 0.U