Added README and Release Notes

README.md

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+FreePDK3 <sup>TM</sup> Predictive Process Design Kit
+=====================================================
+version 1.0 (2021-08-30)
+
+Copyright (c) 2021 North Carolina State University,
+All Rights Reserved.
+
+Please see the file LICENSE in this directory for license.
+You may not use these files except in compliance with the License.
+
+## Welcome to the FreePDK <sup>TM</sup> 3nm Free, Open-Source Process Design Kit 
+
+This initiative is brought to you by NC State Univeristy and Synopsys.
+
+This version of the kit was created by the following at NC State University:
+* Sushant Sadangi              - Design Rules, Layer Stack, and ICV Rules
+* Viswanatha Pasumarthy        - Star-RC Models
+* W. Shepherd Pitts            - HSPICE Models
+* W. Rhett Davis               - Custom Compiler Support and Project Management
+
+Many thanks to the following at Synopsys for technical and financial support:
+* Ron Duncan                      - Process technology advice and ICV Support
+* Luis Francisco & Yen-Sung Chen  - ICV Rules Templates and Coding Support
+* Olaf Schneider                  - Custom Compiler PDK and Scripting Support
+* Jonathan White & Patrick Haspel - Project Management
+
+
+## Quick Design Kit Usage Instructions
+
+  1) Create or modify the file lib.defs in your current directory
+     and ensure that it includes the following line:
+
+          INCLUDE $PDK_DIR/syncust/lib.defs
+
+     ...where $PDK_DIR is replaced with the path to the directory
+     containing this file.  Note that the environmnet variable
+     PDK_DIR does not need to be set.
+
+  2) Source your setup scripts for Synopsys Custom Compiler, IC Validator,
+     Star-RC, HSPICE, and Custom WaveView
+
+  3) Start Synopsys Custom Compiler with the command `custom_compiler &`
+
+## Contents 
+
+| Directory  | Contents                                                       |
+| ---------- | -------------------------------------------------------------- |
+| syncust/   | Technology libraries and scripts for Synopsys Custom Compiler  |
+| icv/       | DRC and LVS rules for Synopsys IC Validator                    |
+| starrc/    | Parasitic extraction models for Synopsys StarRC                |
+| hspice/    | Simulation models for Synopsys HSPICE                          |
+| examples/  | Example library with layouts and schematics                    |
+| doc/       | Design Rule Manual and Release Notes                           |
+
+
+More documentation and tutorials for this kit
+can be found at <http://www.eda.ncsu.edu/FreePDK>
+
+*Please send all questions and comments to <[email protected]>*
+
+

doc/FreePDK3_Release_Notes.md

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+FreePDK3 Release Notes
+======================
+
+## Version 1.0 (2021-08-30)
+
+* Included in this release
+  * Technology library and display resources for Synopsys Custom Compiler
+      (Tested with Custom Compiler Q-2020.03-SP2)
+  * IC Validator DRC & LVS Rules (Tested with ICV R-2020.09)
+  * StarRC extraction Models (Tested with StarRC R-2020.09)
+  * HSPICE Simulation Models (Tested with HSPICE Q-2020.03-SP2)
+* Issues with this release
+  * Design Rules
+    * The ANTENNA rule is implemented, but no protection-diode structure 
+	     exists.  Therefore, some other means to fix the violation would be 
+	     required for long run lengths (such as "stapling" to a lower metal 
+	     layer).  We plan to release an updated kit with a protection-diode.  
+      Until then, this rule can be disabled by editing the file 
+      icv/FreePDK3_main.drc.rs by inserting comment characters "//" in 
+	     front of the line that includes FreePDK3.antenna.drc.rs.
+	* Preliminary double patterning rules have been added for metal layers
+	  1-3 and 7-9.  Rule Mx.7 decomposes each layer into two masks and
+	  stores the result in a file called m#_dpt_output.gds.  Rule Mx.8 
+	  checks to ensure that density requirements are met.  These rules 
+	  are otherwise undocumented, buecause we are still tuning them and 
+	  expect them to change in a future release.
+  * Circuit Simulation Models
+    * Preliminary HSPICE models have been added, based on a simple 
+	     Sentaurus simulation.  This model includes a single nanosheet wrapped
+	     in gate metal with no source or drain regions.  Our simulations are
+	     showing much better performance than we would have expected, so please
+	     use these models only as a first glimpse of a gate-all-around FET.  
+	     More work is needed to properly tune these models.  Please contact us
+	     if you would like to help with this task.
+  * Parasitic Extraction Models
+    * StarRC extraction models are also are provided for a typical process.
+      We anticipate supporting corner models in a future release.
+	* StarRC models are complete down to the V0A layer, but the lower layers
+	  need additional work.  In particular, we anticipate one or more of
+	  the following changes in a future release:
+	  * Separate GATE layers in ICV LVS rules for device and field,
+	    with the LAYER_TYPE properly set, to avoid double-counting the GATE capacitance (Rule 2, p. 8-13 in StarRC User Guide)
+	  * a MULTIGATE statement to model the gate all around the nanosheet 
+	    (p. 12-4 in StarRC User Guide)
+	  * TRENCH_CONTACT layer-types to properly model the M0A layer
+	  * Proper modeling of the conformal dielectric of the buried power-rail
+     to capture substrate coupling capacitance