sim: Update encodings for SYNC,CCTRL,CRC32* and add WAIT

mrisc32 · Mar 21, 2023 · 9fe9342 · 9fe9342
1 parent 91654a9
commit 9fe9342
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Showing 2 changed files with 9 additions and 4 deletions.
diff --git a/sim/cpu.hpp b/sim/cpu.hpp
@@ -168,10 +168,11 @@ class cpu_t {
   static const uint32_t EX_OP_FUNPH = 0x017du;
   static const uint32_t EX_OP_FSQRT = 0x087du;
 
-  static const uint32_t EX_OP_SYNC = 0x007eu;
-  static const uint32_t EX_OP_CCTRL = 0x017eu;
-  static const uint32_t EX_OP_CRC32C = 0x027eu;
-  static const uint32_t EX_OP_CRC32 = 0x037eu;
+  static const uint32_t EX_OP_WAIT = 0x007eu;
+  static const uint32_t EX_OP_SYNC = 0x017eu;
+  static const uint32_t EX_OP_CCTRL = 0x027eu;
+  static const uint32_t EX_OP_CRC32C = 0x087eu;
+  static const uint32_t EX_OP_CRC32 = 0x097eu;
 
   // Memory operations.
   static const uint32_t MEM_OP_NONE = 0x0u;

diff --git a/sim/cpu_simple.cpp b/sim/cpu_simple.cpp
@@ -2671,6 +2671,10 @@ uint32_t cpu_simple_t::run(const uint32_t start_addr, const int64_t max_cycles)
                     ex_result = fsqrt32(src_a, src_b);
                 }
                 break;
+              case EX_OP_WAIT:
+                // Not much to do here.
+                ex_result = 0U;
+                break;
               case EX_OP_SYNC:
                 // Not much to do here.
                 ex_result = 0U;