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Make ISA definitions compile-time defined. #315

Merged
merged 102 commits into from
Nov 9, 2023
Merged

Make ISA definitions compile-time defined. #315

merged 102 commits into from
Nov 9, 2023

Commits on Nov 9, 2023

  1. Redefine instruction classes with templates 

    They have also been moved to the ISA library.
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  2. Move over existing comments

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  3. Add RISC-V opcode type

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  4. Add some RISC-V instruction types

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  5. Reimplement AddI instruction as a type 

    Also fixed compiler errors.
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  6. Add prefixes to differentiate between types

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  7. Run clang-format 

    Turns out QtCreator was set to only format *.hpp headers instead of *.h
:P
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  8. Add constructor for RVI ISA

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  9. Test out static bitfield lookup

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  10. Move some types around and fixup assembler functions

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  11. Checkpoint (a lot of stuff in this commit)

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  12. Add back verification functions for instructions

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  13. Move some more functions around and change RVISA to a struct

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  14. Fix some assembler errors

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  15. Move some more types around and add compile-time field verification

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  16. Rewriting the ISAInterface

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  17. Rewrote most of the ISA interface as static functions

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  18. Finished initial templates for ISA/Assembler libraries 

    This commit finally gets everything to actually build! Though it does
sigfault on startup when it fails to disassemble anything. Next up is
actually implementing the assembler functions...
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  19. Add PseudoLoad instructions

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  20. Use existing ISA enum as template parameter

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  21. Use base classes for BitRange and OpPart 

    Also change static methods to be capitalized in instruction.h
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  22. Go back to virtual function-based ISAInfoBase implementation 

    I tried to get all the ISA info to be implemented in static functions so
they can be called from anywhere, but it ended up not working well. When
the ISA needs extensions to be defined at compile-time, then all the
possible combinations of extensions would also need to be defined at
compile-time. This proved to be too inconvenient, so the extensions are
defined as a runtime vector instead.
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  23. Fix segfaults from improper array initialization

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  24. Fix instruction field assembly functions 

    They were using the wrong token index :)

Also flipped an invalid boolean expression
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  25. Remove unused code and files

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  26. Run clang-format on all changed files

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  27. Add back some error checking

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  28. Fix field errors not showing up in the editor

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  29. Fix OpPart ordering and re-implement ANDI instruction

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  30. Remove unnecessary using statements

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  31. Create template functions for easily enabling instructions 

    Also changed RISC-V ExtI from a struct to a namespace. Needed to link
the assembler lib to the ISA lib to fix missing function definitions.
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  32. Shorten instruction classes by moving funct3 to a template parameter

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  33. Add rest of I-Type instructions

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  34. Add IShift-Type instructions and remove assertions that dont work well

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  35. Add TODOs for future compile-time verifications

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  36. Add static assertion to ensure BitRanges do not overlap 

    Needs another assertion to ensure opcodes dont overlap with fields.
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  37. Add static assertion for OpPart to ensure value fits in the bitrange 

    Also add option for 64-bit shift variants in instruction set
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  38. Add 64-bit IShift-Type variants

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  39. Use 64-bit options in RV64 assembler

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  40. Add static assertion that instruction fields are valid 

    Ensures:

* The fields are ordered from [0 - (N-1)] where N is the number of fields
* The first field has index 0
* There are no skipped indices
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  41. Add static assertion for ImmPart to ensure it fits in the register width

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  42. Verify that ImmParts do not overlap when constructing an immediate

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  43. Add verification for all bitranges in an instruction 

    Ensures bitranges in the Fields don't overlap with bitranges in the
Opcode.
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  44. Add verification to ensure Immediate's width matches BitRanges

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  45. Add verifications for full instructions 

    Ensures all bits are utilized and that bitranges from the Fields don't
overlap with bitranges from the Opcode.
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  46. Change Instruction and Reg names from QString to std::string_view

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  47. Re-implement L-Type instructions

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  48. Re-implement ECALL instruction 

    Had to fix some parts of the class structure so that FieldsImpl works
when there are no fields.
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  49. Re-implement auipc and lui. Also fix width verification for immediates

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  50. Re-implement JAL instruction

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  51. Add template parameter verification for BitRangesImpl

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  52. Add comments and add BitRange type assertion

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  53. Re-implement all I-extension instructions

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  54. Re-implement most pseudo-instructions for I-extension

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  55. Add more pseudoinstructions

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  56. Fix Funct6 encoding for I-Shift64 instructions

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  57. Re-implement M-extension instructions

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  58. Start re-implementing compressed RISC-V instruction set 

    NOTE: This commit does not have instruction matching working for the
re-implemented instructions. For some reason, the assembler will not
match compressed instructions. I'm guessing it has something to do with
the smaller instruction size.
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  59. Update TODOs

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  60. Assert instructions are byte-aligned at compile-time

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  61. Refactor instruction verifications

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  62. Refactor FieldSet to assign field indices automatically 

    FieldSet was renamed from FieldsImpl
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  63. Refactor instruction fields definition to shorten implementation

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  64. Shorten instruction opcode definitions

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  65. Simplify class structure for BitRange and OpPart

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  66. Move instruction byte size out of verification class

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  67. Add OpPart type verification

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  68. Add Field template type verification

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  69. Remove unused code

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  70. Remove unnecessary TODOs

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  71. Re-implement CI-Type instructions

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  72. Re-implement c.nop

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  73. Re-implement CSS-Type instructions

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  74. Re-implement CL-Type instructions

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  75. Re-implement CS-Type instructions

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  76. Re-implement J-Type instructions

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  77. Fix assertion accidentially firing under certain conditions 

    It would wrongly cause a crash when a compressed instruction was the
last instruction of a program and it needed linkage to a symbol.
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  78. Re-implement CB-Type instructions

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  79. Re-implement c.addi4spn

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  80. Re-implement CR-Type instructions

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  81. Re-implement CR2-Type instructions

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  82. Re-implement c.ebreak and fix collision with c.jalr

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  83. Try to fix compiler errors

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  84. Try to fix MSVC compiler error

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  85. Update clang-format PR check to not throw errors when files are removed

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  86. Remove commented out code

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  87. Add missing comment

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  88. Remove unused ISA-specific code

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  89. Add description for template parameter _N

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  90. Fix IndexedOpPart struct to remove unnecessary function

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  91. Add missing assert message

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  92. Remove duplicate functions from BitRange

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  93. Fix camelCase in BitRangeSet

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  94. Fix OpPartBase, OpPart, and OpPartSet

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  95. Fix Field, FieldSet, Reg, and ImmBase 

    Fixed camelCase and removed unnecessary functions
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  96. Rename ImmPartsImpl to ImmPartSet and fix camelCase

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  97. Fix more camelCase

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  98. Remove ISA-specific function gprRegInfo()

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  99. Add TODOs to decouple vsrtl library

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  100. Update VSRTL

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  101. Replace getInstance() with normal constructor

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  102. Remove 'GPR' from struct name

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