Investigation: Does templating the entire assembler infra on register width really matter? #311
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This was referenced Oct 6, 2023
mortbopet
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Nov 9, 2023
Changed ISA code structure to use template classes for instruction information. This information is now defined at compile-time, instead of dynamically at runtime. In this change, all information about an instruction (opcode parts, fields, bit ranges, etc.) is initialized using template parameters. ## Issues Solved This almost fully solves #306 by using template parameters to define instruction set information at compile-time instead of runtime. The only remaining thing to do here is group up instruction sets at compile-time instead of dynamically. As of this change, instruction sets are created at runtime in the `enableInstructions()` function depending on which extensions are enabled. To solve this, each ISA extension could have a struct that uses template parameters to define the extension's enabled instructions at compile-time. These structs can then be combined at run-time depending on which extensions are enabled. I have not tested this yet, but I think it would work and be an improvement over defining the enabled instructions in the `enableInstructions()` function. This almost solves #303. ISA-specific information such as instruction encodings, register information, and other details have all been moved to the ISA library. The only remaining ISA-specific information are the RV32 and RV64 assembler classes and RISC-V relocation functions. The assembler classes are mostly boilerplate code that enables certain instructions based on which extensions are enabled. These assemblers should be replaced by a single assembler class that takes an ISA ID as input. The extensions should be detected (and instructions enabled) only in the ISA library. The relocation functions are short and should be moved to the ISA library as well. Similarly, this almost solves #307. The main problem here is decoupling the ISA/assembler libraries from VSRTL and QT. VSRTL has only a few coupled functions, but there are many dependencies on QT classes. These problems need to be solved before the ISA/assembler libraries can be extracted. #311 has been solved. It is true that register widths do not need to be scattered throughout many template parameters and that removing them cleans up the code base without affecting performance. This change moves register widths into 2 locations; a function called `bits()` in all `ISAInfo` sub-classes (of which there is one per ISA), and the `N` template parameter in the `BitRange` class. Although `N` keeps the register width as a template parameter, it is not as scattered throughout the code base because each ISA uses their own default parameter for `N` equal to the ISA's register width. For example, in the RISC-V C extension file: ```c++ template <unsigned start, unsigned stop> using BitRange = Ripes::BitRange<start, stop, 16>; ``` ## Future Changes There are also a few other improvements that can be made after this change. One is in the `RegInfoBase` class that (as of this change) defines information about all of the registers for an ISA. Although it didn't make it in time for this commit, I've been working on changing this class so that it defines a single register file of an ISA. There will then be a `RegInfoSet` class that holds all of the currently enabled register files for an ISA. This will allow indexing into registers from either a specific register file or all enabled register files as a whole. Another improvement is adding more compile-time instruction verifications. When instructions are combined into a struct at compile-time, as described above, it can be verified at compile-time that there are no duplicate instructions or instruction mnemonics. Other similar verifications could be added to further ensure that ISA implementations are correct. Finally, I think that the implementation for pseudo-instructions could be improved by defining the instructions that they expand into at compile-time. Currently, the `PseudoInstruction` method `expander()` defines what the pseudo-instruction expands to, at runtime. Although I have not tested it yet, I think that this could be improved by changing the `expander()` function into a struct containing the expanded instructions (defined at compile-time).
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Fixed in 2a042c9 |
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Currently, all of the assembler and related logic is templated on types that match the register width of the target architecture (e.g.
uint32_tfor 32-bit,uint64_tfor 64-bit) - and someplace also instruction width.This absolutely infects all of the related code, which usually is an indication that it's not a good design pattern, e.g.:
https://github.com/mortbopet/Ripes/blob/master/src/assembler/assembler.h#L61-L76
It would be interesting to see whether providing register width dynamically would only be a neglible slowdown as opposed to the current implementation. If so, I personally think it's a valid tradeoff, given that we can simplify a bunch of code and remove templates.
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