Merge pull request #52 from marnovandermaas/code_cleanup

Code cleanup
microsoft · Oct 17, 2024 · 2c4ebf5 · 2c4ebf5
2 parents eedb0ac + df72504
commit 2c4ebf5
Show file tree

Hide file tree

Showing 2 changed files with 8 additions and 11 deletions.
diff --git a/rtl/cheri_ex.sv b/rtl/cheri_ex.sv
@@ -195,7 +195,6 @@ module cheri_ex import cheri_pkg::*; #(
 
   full_cap_t     setaddr1_outcap, setbounds_outcap;
   logic  [15:0]  cheri_wb_err_info_q, cheri_wb_err_info_d;
-  logic  [11:0]  cheri_ex_err_info_q, cheri_ex_err_info_d;
   logic          set_bounds_done;
 
   logic   [4:0]  cheri_err_cause, rv32_err_cause;
@@ -1015,7 +1014,6 @@ module cheri_ex import cheri_pkg::*; #(
     if (!rst_ni) begin
       cheri_wb_err_q      <= 1'b0;
       cheri_wb_err_info_q <= 'h0;
-      cheri_ex_err_info_q <= 'h0;
     end else begin
       // Simple flop here works since
       //  -- cheri_wb_err is gated by cheri_exec_id/ex_valid
@@ -1024,7 +1022,6 @@ module cheri_ex import cheri_pkg::*; #(
       //  -- faulted non-load/store instruction can only stay 1 cycle in wb_stage
       cheri_wb_err_q      <= cheri_wb_err_d; 
       cheri_wb_err_info_q <= cheri_wb_err_info_d;
-      cheri_ex_err_info_q <= cheri_ex_err_info_d;
     end
   end
 

diff --git a/rtl/cheri_pkg.sv b/rtl/cheri_pkg.sv
@@ -858,14 +858,14 @@ $display("--- set_bounds:  b1 = %x, t1 = %x, b2 = %x, t2 = %x", base1, top1, bas
   // permission violations
   parameter int unsigned W_PVIO = 8;
 
-  parameter logic [3:0] PVIO_TAG   = 4'h0;
-  parameter logic [3:0] PVIO_SEAL  = 4'h1;
-  parameter logic [3:0] PVIO_EX    = 4'h2;
-  parameter logic [3:0] PVIO_LD    = 4'h3;
-  parameter logic [3:0] PVIO_SD    = 4'h4;
-  parameter logic [3:0] PVIO_SC    = 4'h5;
-  parameter logic [3:0] PVIO_ASR   = 4'h6;
-  parameter logic [3:0] PVIO_ALIGN = 4'h7;
+  parameter logic [2:0] PVIO_TAG   = 3'h0;
+  parameter logic [2:0] PVIO_SEAL  = 3'h1;
+  parameter logic [2:0] PVIO_EX    = 3'h2;
+  parameter logic [2:0] PVIO_LD    = 3'h3;
+  parameter logic [2:0] PVIO_SD    = 3'h4;
+  parameter logic [2:0] PVIO_SC    = 3'h5;
+  parameter logic [2:0] PVIO_ASR   = 3'h6;
+  parameter logic [2:0] PVIO_ALIGN = 3'h7;
 
 
   function automatic logic [4:0] vio_cause_enc (logic bound_vio, logic[W_PVIO-1:0] perm_vio_vec);