"INSTALLATION OF OPENLANE AND SKYWATER PDK 130"

Minimal requirements for OpenLane:
Docker 19.03.12+
GNU make
Python 3.6+ with PIP
Click,Pyyaml 
Setting up OPenLane
Clone OpenLane repository with Skywater PDK 130 as follows

    git clone https://github.com/The-OpenROAD-Project/OpenLane.git


The default PDK installation directory is $PWD/pdks. If any other location is required then add the configuration variable to bashrc as follows
export PDK_ROOT=/usr/devel/pdks/
Any other path can also be chosen for PDK installation. 

The default SCL to be installed is sky130_fd_sc_hd.
To change that, you can add this configuration variable: export STD_CELL_LIBRARY=<Library name, i.e. sky130_fd_sc_ls>, where the library name is one of:
sky130_fd_sc_hd
sky130_fd_sc_hs
sky130_fd_sc_ms
sky130_fd_sc_ls
sky130_fd_sc_hdll


For intallation of Skywater PDK and OpenLane use the OpenLane make utility just type make inside the cloned OpenLane repo or do 
as following:
    cd OpenLane/
    make openlane
    
This will clone the specific version of Skywater PDK and will pull and will build Docker Container. 
If everything is properly installed by the makefile it will report the success.
In order to test the OpenLane flow and PDK installation just run 
"make test"

This will run a 5 mins test that will verify the OpenLane and Skywater PDK installation and will report success if everything has been successfully installed.

"OPENLANE FLOW FOR MACRO HARDENING FROM AN HDL DESIGN"

OpenLane Flow for Macro Hardening of a test design

Step 1: Copy all HDL files in one folder and name it as 'src' folder.
Step 2: Make a folder inside <OpenLane installation directory>/designs/. The name of the folder is the name of your design and it should be the same as the name of the top level module of your design.
Step 3: Start Docker container of OpenLane by running 

"make mount"

in the terminal.After starting Docker container in the terminal run following tcl script in order to generate a design configuration of your design.

	"flow.tcl -design design1 -init_design_config" 

Step 4: This tcl script will generate a default tcl configutaion file of your design. This "config.tcl" file has following environment variables by default that can be modified.

1. Clock signal name. Make sure that this name matches the name of the clock signal in your top level module.

2. Design name. This should be the same as your top level module name is.

3. Verilog Files. This environment variable should point to all of your HDL files. e.g., set ::env(VERILOG_FILES) "src/*.vh src/*.v"

4. Standard Cell Library. 

Step 5: After making necessary changes to config.tcl file. Run following tcl command. 
	"flow.tcl -design design1 -tag first_run" 
Tag here is the tag of the design run. 	
This will go through all the following steps inorder to generate GDSII file from HDL input files.

"Synthesis"
yosys - Performs RTL synthesis
abc - Performs technology mapping

"OpenSTA" 
Performs static timing analysis on the resulting netlist to generate timing reports

"Floorplan and PDN"
init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
ioplacer - Places the macro input and output ports
pdn - Generates the power distribution network
tapcell - Inserts welltap and decap cells in the floorplan

"Placement"
RePLace - Performs global placement
Resizer - Performs optional optimizations on the design
OpenDP - Perfroms detailed placement to legalize the globally placed components

"CTS"
TritonCTS - Synthesizes the clock distribution network (the clock tree)

"Routing"
FastRoute - Performs global routing to generate a guide file for the detailed router
CU-GR - Another option for performing global routing.
TritonRoute - Performs detailed routing
SPEF-Extractor - Performs SPEF extraction

"GDSII Generation"
Magic - Streams out the final GDSII layout file from the routed def
Klayout - Streams out the final GDSII layout file from the routed def as a back-up

"Checks"
Magic - Performs DRC Checks & Antenna Checks
Klayout - Performs DRC Checks
Netgen - Performs LVS Checks
CVC - Performs Circuit Validity Checks

After all the processes mentioned above are successfully completed without any fatal errors and warnings and GDSII is generated. Go to the runs/first_run/ folder. Here Reports and Results folders will have all reports and results generated by all of the above mentioned steps.