[clkmgr] Deglitch shadow storage error for MAIN clock domain

[andreaskurth]

This is an ECO on the earlgrey_1.0.0 branch that adds a deglitcher on the err_storage output signal for the shadowed measurement control registers related only to the MAIN clock domain. For the IO_DIV4 clock domain, this deglitcher is not required (because the register and the alert sender are clocked with the IO_DIV4 clock), and the other clock domains (IO, IO_DIV2, and USB) are less critical and out of scope of this ECO.

On the master branch, a separate PR will add a deglitcher on the registers for all clock domains (even IO_DIV4, for simplicity).

[andreaskurth]

util/dvsim/dvsim.py hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson --select-cfgs clkmgr -i clkmgr_{smoke,frequency{,_timeout}} passes 100%.

[andreaskurth]

CHANGE AUTHORIZED: hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv

ECO in progress; will be reverted if not successful.

[vogelpi]

LGTM, thanks @andreaskurth !
Thanks for the clear description, the plan sounds very reasonable to me.

[vogelpi]

CHANGE AUTHORIZED: hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv

[andreaskurth]

Waiting for #24624 to land first, so that a tag can be created before this PR is merged

[vogelpi]

This is related to #24592 .