[csrng/rtl] Make the main SM error test signal fatal

[h-filali]

The main SM error test signal is currently the only test signal where the actual error would be fatal but the test signal is not. This commit make adds the err_code_test_bit for the main SM error to fatal_loc_events to make the main SM error test fatal.

[vogelpi]

Thanks for flagging this @h-filali . This looks good to me!

The fix is very small and fully aligns EDN, CSRNG and ENTROPY_SRC with respect to error signaling. I think we should absorb this change but we'll need to discuss this with other leads.

[vogelpi]

CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_core.sv

[rswarbrick]

Is there a reason not to use main_sm_err_sum here? That way, we don't have the magic "21" index in two different places.

[h-filali]

Is there a reason not to use main_sm_err_sum here? That way, we don't have the magic "21" index in two different places.

Yes, there is a reason. main_sm_err_sum causes a loop, since it is set to high by the error signal that comes out of the main SM. And if main_sm_err_sum is high, it in turn causes the main SM error signal to go high. There is a comment above the lines I changed which tries to explain this. Should I maybe make the comment more clear?

[rswarbrick]

Oh, now I understand the comment above. Maybe it would be worth tweaking it slightly to be something like this?

"Rather than using man_err_sum for the main state machine error, we use the error code test bit (index 21), which avoids causing a loop."

But this looks sensible otherwise. Thanks for the response.

UPDATE: ... and now I've read the comment before. Maybe the right fix is change that last sentence to something like:

"To include the state machine error at all, we use the error code test bit (index 21) directly."

[rswarbrick]

CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_core.sv

[h-filali]

@rswarbrick I updated the comment following your suggestion. Thanks for your feedback!

[rswarbrick]

Perfect, thanks!