[keymgr] Don't update and reseed PRNG in Disabled/Invalid state forever

[vogelpi]

Previously, keymgr would keep updating and reseeding the PRNG forever once entering the StCtrlDisabled or StCtrlInvalid state. This is not ideal from an entropy and power consumption viewpoint.

This commit changes the design to - once one of the two states is entered - to keep updating the PRNG (which also triggers the reseed operation) until two more PRNG reseed operation have happened.

This resolves #22997.

FYI, once in the Invalid or Disabled state and after having stopped PRNG update requests inside the main controller, it's still possible that the PRNG is advanced and that reseed operations are started. E.g. if there are still some handshakes on the KMAC app interface or on the sideload ports (see figure below). However, once in the Disabled state, those are not going to be constantly active as before this commit. I think this should be okay.

[vogelpi]

I ran a full regression and results look good. I've compared the reported failures with recent nighly runs and there are no new failure signatures.

KEYMGR Simulation Results

Monday May 13 2024 07:18:52 UTC

GitHub Revision: 69c572b503

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.283m	11.929ms	50	50	100.00 %
V1	random	keymgr_random	1.723m	10.484ms	50	50	100.00 %
V1	csr_hw_reset	keymgr_csr_hw_reset	2.140s	21.757us	5	5	100.00 %
V1	csr_rw	keymgr_csr_rw	5.250s	27.647us	20	20	100.00 %
V1	csr_bit_bash	keymgr_csr_bit_bash	24.100s	3.564ms	5	5	100.00 %
V1	csr_aliasing	keymgr_csr_aliasing	25.900s	1.101ms	5	5	100.00 %
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	7.890s	183.657us	20	20	100.00 %
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	5.250s	27.647us	20	20	100.00 %
		keymgr_csr_aliasing	25.900s	1.101ms	5	5	100.00 %
V1		TOTAL			155	155	100.00 %
V2	cfgen_during_op	keymgr_cfg_regwen	2.668m	13.905ms	49	50	98.00 %
V2	sideload	keymgr_sideload	1.183m	5.489ms	50	50	100.00 %
		keymgr_sideload_kmac	53.760s	1.461ms	50	50	100.00 %
		keymgr_sideload_aes	1.782m	4.115ms	50	50	100.00 %
		keymgr_sideload_otbn	1.592m	2.804ms	50	50	100.00 %
V2	direct_to_disabled_state	keymgr_direct_to_disabled	59.540s	3.859ms	50	50	100.00 %
V2	lc_disable	keymgr_lc_disable	1.479m	2.568ms	49	50	98.00 %
V2	kmac_error_response	keymgr_kmac_rsp_err	19.660s	229.416us	49	50	98.00 %
V2	invalid_sw_input	keymgr_sw_invalid_input	36.570s	1.082ms	50	50	100.00 %
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.190m	3.177ms	50	50	100.00 %
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	10.580s	523.606us	50	50	100.00 %
V2	stress_all	keymgr_stress_all	15.258m	88.050ms	47	50	94.00 %
V2	intr_test	keymgr_intr_test	2.960s	18.447us	50	50	100.00 %
V2	alert_test	keymgr_alert_test	4.410s	70.596us	50	50	100.00 %
V2	tl_d_oob_addr_access	keymgr_tl_errors	16.650s	672.530us	20	20	100.00 %
V2	tl_d_illegal_access	keymgr_tl_errors	16.650s	672.530us	20	20	100.00 %
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.140s	21.757us	5	5	100.00 %
		keymgr_csr_rw	5.250s	27.647us	20	20	100.00 %
		keymgr_csr_aliasing	25.900s	1.101ms	5	5	100.00 %
		keymgr_same_csr_outstanding	15.320s	91.913us	20	20	100.00 %
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.140s	21.757us	5	5	100.00 %
		keymgr_csr_rw	5.250s	27.647us	20	20	100.00 %
		keymgr_csr_aliasing	25.900s	1.101ms	5	5	100.00 %
		keymgr_same_csr_outstanding	15.320s	91.913us	20	20	100.00 %
V2		TOTAL			734	740	99.19 %
V2S	sec_cm_additional_check	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	tl_intg_err	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
		keymgr_tl_intg_err	24.880s	150.248us	20	20	100.00 %
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	14.220s	504.211us	20	20	100.00 %
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	14.220s	504.211us	20	20	100.00 %
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	14.220s	504.211us	20	20	100.00 %
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	14.220s	504.211us	20	20	100.00 %
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	30.630s	655.683us	20	20	100.00 %
V2S	prim_count_check	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	prim_fsm_check	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	24.880s	150.248us	20	20	100.00 %
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	14.220s	504.211us	20	20	100.00 %
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.668m	13.905ms	49	50	98.00 %
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.723m	10.484ms	50	50	100.00 %
		keymgr_csr_rw	5.250s	27.647us	20	20	100.00 %
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.723m	10.484ms	50	50	100.00 %
		keymgr_csr_rw	5.250s	27.647us	20	20	100.00 %
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.723m	10.484ms	50	50	100.00 %
		keymgr_csr_rw	5.250s	27.647us	20	20	100.00 %
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	1.479m	2.568ms	49	50	98.00 %
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.190m	3.177ms	50	50	100.00 %
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.190m	3.177ms	50	50	100.00 %
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.723m	10.484ms	50	50	100.00 %
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.378m	1.097ms	50	50	100.00 %
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.512m	6.342ms	50	50	100.00 %
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	1.479m	2.568ms	49	50	98.00 %
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.512m	6.342ms	50	50	100.00 %
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.512m	6.342ms	50	50	100.00 %
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.512m	6.342ms	50	50	100.00 %
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.800s	1.225ms	5	5	100.00 %
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.512m	6.342ms	50	50	100.00 %
V2S		TOTAL			165	165	100.00 %
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	53.580s	2.700ms	31	50	62.00 %
V3		TOTAL			31	50	62.00 %
		TOTAL			1085	1110	97.75 %

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
  • Test keymgr_stress_all_with_rand_reset has 19 failures.

    • 1.keymgr_stress_all_with_rand_reset.106110215403027291618186750158598098456832650283723424455694519520507871499506
      Line 631, in log /home/pirmin/ot/opentitan/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 205271099 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to i
      

ssue a reset with no outstanding accesses.
UVM_INFO @ 205271099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

    * 4.keymgr_stress_all_with_rand_reset.108153935044028024322969877018842087114356503247959239607979456775585177074495\
      Line 313, in log /home/pirmin/ot/opentitan/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log

            UVM_ERROR @ 512425413 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to i

ssue a reset with no outstanding accesses.
UVM_INFO @ 512425413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

    * ... and 17 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

  • Test keymgr_lc_disable has 1 failures.

    • 3.keymgr_lc_disable.40868107286240535119666083053426801470160408816447687099265493941214508462986
      Line 323, in log /home/pirmin/ot/opentitan/scratch/master/keymgr-sim-vcs/3.keymgr_lc_disable/latest/run.log

        UVM_ERROR @  92379964 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
        UVM_INFO @  92379964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 29.keymgr_stress_all.106211420800583150969664978478751590261782817571614813877356298984269648280690
      Line 1904, in log /home/pirmin/ot/opentitan/scratch/master/keymgr-sim-vcs/29.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 2115377028 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 2115377028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 37.keymgr_kmac_rsp_err.98066386030125023271117272657842045837615282362114735291464703789736696035570
      Line 86, in log /home/pirmin/ot/opentitan/scratch/master/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @   4226801 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @   4226801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StCreatorRootKey for Seali ng Kmac has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 1.keymgr_stress_all.91520647892802646433034516793891701573373226726261873442467981732964049523478
      Line 300, in log /home/pirmin/ot/opentitan/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 221194538 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (3376611288350056895191954645584
      

564291372054256000961267143655111753400603552334852172726507341567084729461578198818581112695660220029987371291856880192771 [0x4078883cb4a30a5bf97a600045f7b20833297e2335924e4d0be37b92a2b
5d076b2d57a83069b7893d2274b64963555f82196a70e524f52207d839eead802cd03] vs 3376611288350056895191954645584564291372054256000961267143655111753400603552334852172726507341567084729461578198
818581112695660220029987371291856880192771 [0x4078883cb4a30a5bf97a600045f7b20833297e2335924e4d0be37b92a2b5d076b2d57a83069b7893d2274b64963555f82196a70e524f52207d839eead802cd03]) KMAC key
at state StCreatorRootKey for Sealing Kmac
UVM_INFO @ 221194538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

• UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac has 1 failures:
  • Test keymgr_stress_all has 1 failures.

    • 12.keymgr_stress_all.15885046883091791011354808538218133753627135052475992723324638483447264681755
      Line 1201, in log /home/pirmin/ot/opentitan/scratch/master/keymgr-sim-vcs/12.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 780693490 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (1297675029124334228350892976660
      

7148735437405236253811157006621942927513168214903152147985330119361741560255193403099100252246705012951083188919631129530818 [0xf7c508be2965b7a8ca553ef08a152e143e11babcfb78802011a409d405
d8b4f53e1995de45e4e7acd096b87f89d44c98bad9790e5d7c6e8f5d9a15448e5ed1c2] vs 129767502912433422835089297666071487354374052362538111570066219429275131682149031521479853301193617415602551934
03099100252246705012951083188919631129530818 [0xf7c508be2965b7a8ca553ef08a152e143e11babcfb78802011a409d405d8b4f53e1995de45e4e7acd096b87f89d44c98bad9790e5d7c6e8f5d9a15448e5ed1c2]) KMAC ke
y at state StDisabled for Attestation Kmac
UVM_INFO @ 780693490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

• UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
  • Test keymgr_cfg_regwen has 1 failures.

    • 43.keymgr_cfg_regwen.26462263629250792743332191976567883198307242577477376663966424026427037892621
      Line 232, in log /home/pirmin/ot/opentitan/scratch/master/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @  16918018 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.s
      

tart
UVM_INFO @ 16918018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

INFO: [FlowCfg] [scratch_path]: [keymgr] [/home/pirmin/ot/opentitan/scratch/master/keymgr-sim-vcs]
ERROR: [dvsim] Errors were encountered in this run.

      [   legend    ]: [Q: queued, D: dispatched, P: passed, F: failed, K: killed, T: total]                                                                                          

00:00:23 [ build ]: [Q: 0000, D: 0000, P: 0001, F: 0000, K: 0000, T: 0001] 100%
00:19:00 [ run ]: [Q: 0000, D: 0000, P: 1085, F: 0025, K: 0000, T: 1110] 100%

[ballifatih]

LGTM, thanks @vogelpi. As far as I see, this change only suppresses the enable signals coming from the controller, therefore any req<->ack interaction between EDN and keymgr_reseed_ctrl is not disturbed. If there is any pending EDN request, regardless of this change, it will still be acknowledged by keymgr_reseed_ctrl.

[vogelpi]

LGTM, thanks @vogelpi. As far as I see, this change only suppresses the enable signals coming from the controller, therefore any req<->ack interaction between EDN and keymgr_reseed_ctrl is not disturbed. If there is any pending EDN request, regardless of this change, it will still be acknowledged by keymgr_reseed_ctrl.

Yes exactly, that is what is happening. Thanks for looking at this and approving it @ballifatih !

[andreaskurth]

LGTM, thx @vogelpi