[i2c] Reduce counter sizes to save area

[a-will]

Reduce counter sizes to only the widths needed to support Standard mode at a 1 GHz core clock.

In the FPGA implementation, this saves 44 flops (~4%) and over 100 LUTs (~6.6%). The granularity of the FPGA area is large, so the size of the savings can be misleading, but compared to what we had prior to the FSM split, this brings us to +29 flops, -59 LUTs for the whole chain of commits.

This builds on #22551. Only the last commit is new.

[andreaskurth]

Thanks for these optimizations, @a-will. Area matters these days :-)

LGTM; I just have suggestions about capturing this in the documentation. (And obviously please only rebase & merge this after the PR that this depends on got merged.)

[a-will]

Ah, kokoro provided results. I'll fix the lint errors.

[jwnrt]

FYI, the //sw/device/tests:rv_dm_access_after_wakeup_dev_fpga_cw310_sival test fails in CI after commit b2239fc38e0725f17b1155d7e48ec6403facf7f6 (but passes before). It must be due to some combination with another commit that was merged before this one since this PR passed CI.

We're not really sure why the test fails yet, but OpenOCD can't connect through JTAG after the chip wakes up from deep sleep:

[2024-04-24T13:57:20.971Z INFO  opentitanlib::debug::openocd::stderr] Error: JTAG scan chain interrogation failed: all ones

[a-will]

Given the content of this PR, it is very highly unlikely to be the cause, though.

[jwnrt]

I think you're right. Maybe it's just due to the bitstreams available in the cache before and after this PR merged. Apologies for the noise.