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[flash_ctrl] Pop read pipeline FIFOs for data and mask in sync #22571

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merged 1 commit into from
Apr 16, 2024

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vogelpi
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@vogelpi vogelpi commented Apr 15, 2024

This commit fixes a bug in the read pipeline where the data and the mask storage FIFO could get out of sync in case of the mask computation running behind the actual Flash read (e.g. due to back pressure in the shared scrambling logic).

To avoid the FIFOs getting out of sync, the design now tracks whether for reads that don't require descrambling, a mask was still computed. This can happen if for scramble enabled locations that are being erased. In case a mask computation has been started, the FIFOs are now only popped if both the data and the mask FIFO contain a valid entry (i.e. the mask computation for the data to be popped has finished).

This resolves #22443

This commit fixes a bug in the read pipeline where the data and the mask
storage FIFO could get out of sync in case of the mask computation
running behind the actual Flash read (e.g. due to back pressure in the
shared scrambling logic).

To avoid the FIFOs getting out of sync, the design now tracks whether
for reads that don't require descrambling, a mask was still computed.
This can happen if for scramble enabled locations that are being erased.
In case a mask computation has been started, the FIFOs are now only
popped if both the data and the mask FIFO contain a valid entry (i.e.
the mask computation for the data to be popped has finished).

This resolves lowRISC#22443

Signed-off-by: Pirmin Vogel <[email protected]>
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@matutem matutem left a comment

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Looks good. I am afraid this interface is getting a bit messy. Do you think it should be implemented by a state machine or in some other cleaner fashion at some point?

@vogelpi
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vogelpi commented Apr 16, 2024

Thanks @matutem !

Regarding implementing a state machine for this: I don't know if this would improve things to be honest as the read pipeline is pipelined: Multiple requests can be in flight and there is even a small cache. I believe this is always going to be a bit messy. What would maybe help is a more thorough cleanup (of code and comments - some are no longer aligned with the RTL) but I fear this would introduce risk again which is undesirable at this stage.

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vogelpi commented Apr 16, 2024

Regression results are here, things look good:

### Test Results                                                                                                                                                                                                          [84/460]
|  Stage  |                   Name                    | Tests                                    |  Max Job Runtime  |  Simulated Time  |  Passing  |  Total  |  Pass Rate  |                                                     
|:-------:|:-----------------------------------------:|:-----------------------------------------|:-----------------:|:----------------:|:---------:|:-------:|:-----------:|                                                     
|   V1    |                   smoke                   | flash_ctrl_smoke                         |      4.487m       |     22.651us     |    50     |   50    |  100.00 %   |                                                     
|   V1    |                 smoke_hw                  | flash_ctrl_smoke_hw                      |      37.450s      |     16.156us     |     5     |    5    |  100.00 %   |                                                     
|   V1    |               csr_hw_reset                | flash_ctrl_csr_hw_reset                  |      1.078m       |     89.518us     |     5     |    5    |  100.00 %   |                                                     
|   V1    |                  csr_rw                   | flash_ctrl_csr_rw                        |      22.310s      |     59.956us     |    20     |   20    |  100.00 %   |                                                     
|   V1    |               csr_bit_bash                | flash_ctrl_csr_bit_bash                  |      1.039m       |     3.419ms      |     5     |    5    |  100.00 %   |                                                     
|   V1    |               csr_aliasing                | flash_ctrl_csr_aliasing                  |      1.073m       |     5.491ms      |     5     |    5    |  100.00 %   |                                                     
|   V1    |        csr_mem_rw_with_rand_reset         | flash_ctrl_csr_mem_rw_with_rand_reset    |      24.230s      |     42.868us     |    20     |   20    |  100.00 %   |                                                     
|   V1    | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw                        |      22.310s      |     59.956us     |    20     |   20    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_csr_aliasing                  |      1.073m       |     5.491ms      |     5     |    5    |  100.00 %   |                                                     
|   V1    |                 mem_walk                  | flash_ctrl_mem_walk                      |      19.840s      |     48.269us     |     5     |    5    |  100.00 %   |                                                     
|   V1    |            mem_partial_access             | flash_ctrl_mem_partial_access            |      21.200s      |     49.822us     |     5     |    5    |  100.00 %   |                                                     
|   V1    |                                           | **TOTAL**                                |                   |                  |    120    |   120   |  100.00 %   |                                                     
|   V2    |                   sw_op                   | flash_ctrl_sw_op                         |      37.460s      |    122.969us     |     5     |    5    |  100.00 %   |                                                     
|   V2    |             host_read_direct              | flash_ctrl_host_dir_rd                   |      3.002m       |    585.950us     |     5     |    5    |  100.00 %   |                                                     
|   V2    |                 rma_hw_if                 | flash_ctrl_hw_rma                        |      15.281m      |    183.834ms     |     3     |    3    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_hw_rma_reset                  |      9.099m       |    100.150ms     |    20     |   20    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_lcmgr_intg                    |      19.860s      |     15.075us     |    20     |   20    |  100.00 %   |                                                     
|   V2    |            host_controller_arb            | flash_ctrl_host_ctrl_arb                 |      31.732m      |    274.685ms     |     5     |    5    |  100.00 %   |                                                     
|   V2    |               erase_suspend               | flash_ctrl_erase_suspend                 |      8.200m       |     5.185ms      |     5     |    5    |  100.00 %   |                                                     
|   V2    |               program_reset               | flash_ctrl_prog_reset                    |      1.516m       |     12.903ms     |    30     |   30    |  100.00 %   |                                                     
|   V2    |            full_memory_access             | flash_ctrl_full_mem_access               |      34.437m      |    111.521ms     |     5     |    5    |  100.00 %   |                                                     
|   V2    |             rd_buff_eviction              | flash_ctrl_rd_buff_evict                 |      2.834m       |     3.693ms      |     5     |    5    |  100.00 %   |                                                     
|   V2    |          rd_buff_eviction_w_ecc           | flash_ctrl_rw_evict                      |      48.490s      |     59.935us     |    39     |   40    |   97.50 %   |                                                     
|         |                                           | flash_ctrl_rw_evict_all_en               |      49.410s      |    902.962us     |    40     |   40    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_re_evict                      |      48.580s      |    526.072us     |    20     |   20    |  100.00 %   |                                                     
|   V2    |                 host_arb                  | flash_ctrl_phy_arb                       |      9.825m       |     2.884ms      |    20     |   20    |  100.00 %   |                                                     
|   V2    |              host_interleave              | flash_ctrl_phy_arb                       |      9.825m       |     2.884ms      |    20     |   20    |  100.00 %   |                                                     
|   V2    |             memory_protection             | flash_ctrl_mp_regions                    |      8.745m       |     13.141ms     |    20     |   20    |  100.00 %   |                                                     
|   V2    |                fetch_code                 | flash_ctrl_fetch_code                    |      30.110s      |    504.845us     |    10     |   10    |  100.00 %   |                                                     
|   V2    |              all_partitions               | flash_ctrl_rand_ops                      |      26.423m      |     4.758ms      |    20     |   20    |  100.00 %   |                                                     
|   V2    |                 error_mp                  | flash_ctrl_error_mp                      |      40.113m      |     4.068ms      |    10     |   10    |  100.00 %   |                                                     
|   V2    |              error_prog_win               | flash_ctrl_error_prog_win                |      20.149m      |    331.437us     |    10     |   10    |  100.00 %   |                                                     
|   V2    |              error_prog_type              | flash_ctrl_error_prog_type               |      44.486m      |     2.591ms      |     5     |    5    |  100.00 %   |                                                     
|   V2    |              error_read_seed              | flash_ctrl_hw_read_seed_err              |      20.050s      |     27.440us     |    20     |   20    |  100.00 %   |                                                     
|   V2    |            read_write_overflow            | flash_ctrl_oversize_error                |      2.154m       |     4.634ms      |     5     |    5    |  100.00 %   |                                                     
|   V2    |            flash_ctrl_disable             | flash_ctrl_disable                       |      33.430s      |     21.132us     |    50     |   50    |  100.00 %   |                                                     
|   V2    |            flash_ctrl_connect             | flash_ctrl_connect                       |      23.120s      |     13.253us     |    80     |   80    |  100.00 %   |                                                     
|   V2    |                stress_all                 | flash_ctrl_stress_all                    |      28.758m      |     19.916ms     |     5     |    5    |  100.00 %   |                                                     
|   V2    |             secret_partition              | flash_ctrl_hw_sec_otp                    |      2.522m       |     17.545ms     |    50     |   50    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_otp_reset                     |      3.121m       |    400.528us     |    80     |   80    |  100.00 %   |                                                     
|   V2    |            isolation_partition            | flash_ctrl_hw_rma                        |      15.281m      |    183.834ms     |     3     |    3    |  100.00 %   |                                                     
|   V2    |                interrupts                 | flash_ctrl_intr_rd                       |      2.605m       |     2.829ms      |    40     |   40    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_intr_wr                       |      1.745m       |     11.321ms     |    10     |   10    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_intr_rd_slow_flash            |      3.323m       |     68.636ms     |    40     |   40    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_intr_wr_slow_flash            |      16.088m      |    888.986ms     |    10     |   10    |  100.00 %   |                                                     
|   V2    |                invalid_op                 | flash_ctrl_invalid_op                    |      1.202m       |     6.068ms      |    20     |   20    |  100.00 %   |                                                     
|   V2    |                mid_op_rst                 | flash_ctrl_mid_op_rst                    |      1.672m       |     3.797ms      |     5     |    5    |  100.00 %   |                                                     
|   V2    |              double_bit_err               | flash_ctrl_read_word_sweep_derr          |      32.110s      |     24.070us     |     5     |    5    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_ro_derr                       |      1.800m       |     2.755ms      |    10     |   10    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_rw_derr                       |      5.618m       |     12.426ms     |    10     |   10    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_derr_detect                   |      2.199m       |    326.896us     |     5     |    5    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_integrity                     |      5.483m       |     4.063ms      |     5     |    5    |  100.00 %   |                                                     
|   V2    |              single_bit_err               | flash_ctrl_read_word_sweep_serr          |      33.910s      |     35.293us     |     5     |    5    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_ro_serr                       |      1.679m       |     2.958ms      |    10     |   10    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_rw_serr                       |      5.537m       |     8.079ms      |    10     |   10    |  100.00 %   |                                                     
|   V2    |           singlebit_err_counter           | flash_ctrl_serr_counter                  |      1.186m       |     3.144ms      |     5     |    5    |  100.00 %   |                                                     
|   V2    |           singlebit_err_address           | flash_ctrl_serr_address                  |      1.090m       |    706.676us     |     5     |    5    |  100.00 %   |                                                     
|   V2    |                 scramble                  | flash_ctrl_wo                            |      2.425m       |     5.206ms      |    20     |   20    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_write_word_sweep              |      20.360s      |    549.122us     |     1     |    1    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_read_word_sweep               |      11.070s      |     27.571us     |     1     |    1    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_ro                            |      1.334m       |     4.194ms      |    20     |   20    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_rw                            |      5.121m       |     33.177ms     |    20     |   20    |  100.00 %   |                                                     
|   V2    |            filesystem_support             | flash_ctrl_fs_sup                        |      35.380s      |    327.529us     |     5     |    5    |  100.00 %   |                                                     
|   V2    |          rma_write_process_error          | flash_ctrl_rma_err                       |      10.152m      |     39.758ms     |     3     |    3    |  100.00 %   |
|         |                                           | flash_ctrl_hw_prog_rma_wipe_err          |      3.443m       |     10.012ms     |    20     |   20    |  100.00 %   |                                             [17/460]
|   V2    |                alert_test                 | flash_ctrl_alert_test                    |      21.510s      |    254.629us     |    50     |   50    |  100.00 %   |                                                     
|   V2    |                 intr_test                 | flash_ctrl_intr_test                     |      21.170s      |     46.302us     |    50     |   50    |  100.00 %   |                                                     
|   V2    |           tl_d_oob_addr_access            | flash_ctrl_tl_errors                     |      24.860s      |     64.442us     |    20     |   20    |  100.00 %   |                                                     
|   V2    |            tl_d_illegal_access            | flash_ctrl_tl_errors                     |      24.860s      |     64.442us     |    20     |   20    |  100.00 %   |                                                     
|   V2    |          tl_d_outstanding_access          | flash_ctrl_csr_hw_reset                  |      1.078m       |     89.518us     |     5     |    5    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_csr_rw                        |      22.310s      |     59.956us     |    20     |   20    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_csr_aliasing                  |      1.073m       |     5.491ms      |     5     |    5    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_same_csr_outstanding          |      40.850s      |    926.465us     |    20     |   20    |  100.00 %   |                                                     
|   V2    |            tl_d_partial_access            | flash_ctrl_csr_hw_reset                  |      1.078m       |     89.518us     |     5     |    5    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_csr_rw                        |      22.310s      |     59.956us     |    20     |   20    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_csr_aliasing                  |      1.073m       |     5.491ms      |     5     |    5    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_same_csr_outstanding          |      40.850s      |    926.465us     |    20     |   20    |  100.00 %   |                                                     
|   V2    |                                           | **TOTAL**                                |                   |                  |   1012    |  1013   |   99.90 %   |                                                     
|   V2S   |          shadow_reg_update_error          | flash_ctrl_shadow_reg_errors             |      23.220s      |     41.875us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |    shadow_reg_read_clear_staged_value     | flash_ctrl_shadow_reg_errors             |      23.220s      |     41.875us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |         shadow_reg_storage_error          | flash_ctrl_shadow_reg_errors             |      23.220s      |     41.875us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |           shadowed_reset_glitch           | flash_ctrl_shadow_reg_errors             |      23.220s      |     41.875us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |    shadow_reg_update_error_with_csr_rw    | flash_ctrl_shadow_reg_errors_with_csr_rw |      21.380s      |     17.405us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |                tl_intg_err                | flash_ctrl_sec_cm                        |      1.614h       |     1.290ms      |     5     |    5    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_tl_intg_err                   |      15.985m      |     4.329ms      |    20     |   20    |  100.00 %   |                                                     
|   V2S   |         sec_cm_reg_bus_integrity          | flash_ctrl_tl_intg_err                   |      15.985m      |     4.329ms      |    20     |   20    |  100.00 %   |                                                     
|   V2S   |         sec_cm_host_bus_integrity         | flash_ctrl_tl_intg_err                   |      15.985m      |     4.329ms      |    20     |   20    |  100.00 %   |                                                     
|   V2S   |         sec_cm_mem_bus_integrity          | flash_ctrl_rd_intg                       |      43.860s      |    991.426us     |     3     |    3    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_wr_intg                       |      21.890s      |    471.656us     |     3     |    3    |  100.00 %   |                                                     
|   V2S   |       sec_cm_scramble_key_sideload        | flash_ctrl_smoke                         |      4.487m       |     22.651us     |    50     |   50    |  100.00 %   |                                                     
|   V2S   |       sec_cm_lc_ctrl_intersig_mubi        | flash_ctrl_otp_reset                     |      3.121m       |    400.528us     |    80     |   80    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_disable                       |      33.430s      |     21.132us     |    50     |   50    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_sec_info_access               |      1.275m       |     7.763ms      |    50     |   50    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_connect                       |      23.120s      |     13.253us     |    80     |   80    |  100.00 %   |                                                     
|   V2S   |         sec_cm_ctrl_config_regwen         | flash_ctrl_config_regwen                 |      20.130s      |    138.108us     |     5     |    5    |  100.00 %   |                                                     
|   V2S   |     sec_cm_data_regions_config_regwen     | flash_ctrl_csr_rw                        |      22.310s      |     59.956us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |     sec_cm_data_regions_config_shadow     | flash_ctrl_shadow_reg_errors             |      23.220s      |     41.875us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |     sec_cm_info_regions_config_regwen     | flash_ctrl_csr_rw                        |      22.310s      |     59.956us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |     sec_cm_info_regions_config_shadow     | flash_ctrl_shadow_reg_errors             |      23.220s      |     41.875us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |         sec_cm_bank_config_regwen         | flash_ctrl_csr_rw                        |      22.310s      |     59.956us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |         sec_cm_bank_config_shadow         | flash_ctrl_shadow_reg_errors             |      23.220s      |     41.875us     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |        sec_cm_mem_ctrl_global_esc         | flash_ctrl_disable                       |      33.430s      |     21.132us     |    50     |   50    |  100.00 %   |                                                     
|   V2S   |         sec_cm_mem_ctrl_local_esc         | flash_ctrl_rd_intg                       |      43.860s      |    991.426us     |     3     |    3    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_access_after_disable          |      19.920s      |     13.894us     |     3     |    3    |  100.00 %   |                                                     
|   V2S   |      sec_cm_mem_disable_config_mubi       | flash_ctrl_disable                       |      33.430s      |     21.132us     |    50     |   50    |  100.00 %   |                                                     
|   V2S   |         sec_cm_exec_config_redun          | flash_ctrl_fetch_code                    |      30.110s      |    504.845us     |    10     |   10    |  100.00 %   |                                                     
|   V2S   |            sec_cm_mem_scramble            | flash_ctrl_rw                            |      5.121m       |     33.177ms     |    20     |   20    |  100.00 %   |                                                     
|   V2S   |           sec_cm_mem_integrity            | flash_ctrl_rw_serr                       |      5.537m       |     8.079ms      |    10     |   10    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_rw_derr                       |      5.618m       |     12.426ms     |    10     |   10    |  100.00 %   |                                                     
|         |                                           | flash_ctrl_integrity                     |      5.483m       |     4.063ms      |     5     |    5    |  100.00 %   |                                                     
|   V2S   |       sec_cm_rma_entry_mem_sec_wipe       | flash_ctrl_hw_rma                        |      15.281m      |    183.834ms     |     3     |    3    |  100.00 %   |                                                     
|   V2S   |          sec_cm_ctrl_fsm_sparse           | flash_ctrl_sec_cm                        |      1.614h       |     1.290ms      |     5     |    5    |  100.00 %   |                                                     
|   V2S   |           sec_cm_phy_fsm_sparse           | flash_ctrl_sec_cm                        |      1.614h       |     1.290ms      |     5     |    5    |  100.00 %   |                                                     
|   V2S   |        sec_cm_phy_prog_fsm_sparse         | flash_ctrl_sec_cm                        |      1.614h       |     1.290ms      |     5     |    5    |  100.00 %   |                                                     
|   V2S   |             sec_cm_ctr_redun              | flash_ctrl_sec_cm                        |      1.614h       |     1.290ms      |     5     |    5    |  100.00 %   |                                                     
|   V2S   |       sec_cm_phy_arbiter_ctrl_redun       | flash_ctrl_phy_arb_redun                 |      1.026m       |    834.667us     |     5     |    5    |  100.00 %   |                                                     
|   V2S   |  sec_cm_phy_host_grant_ctrl_consistency   | flash_ctrl_phy_host_grant_err            |      22.180s      |     41.597us     |     5     |    5    |  100.00 %   |                                                     
|   V2S   |      sec_cm_phy_ack_ctrl_consistency      | flash_ctrl_phy_ack_consistency           |      19.360s      |     16.358us     |     5     |    5    |  100.00 %   |                                                     
|   V2S   |           sec_cm_fifo_ctr_redun           | flash_ctrl_sec_cm                        |      1.614h       |     1.290ms      |     5     |    5    |  100.00 %   |                                                     
|   V2S   |     sec_cm_mem_tl_lc_gate_fsm_sparse      | flash_ctrl_sec_cm                        |      1.614h       |     1.290ms      |     5     |    5    |  100.00 %   |                                                     
|   V2S   |     sec_cm_prog_tl_lc_gate_fsm_sparse     | flash_ctrl_sec_cm                        |      1.614h       |     1.290ms      |     5     |    5    |  100.00 %   |                                                     
|   V2S   |                                           | **TOTAL**                                |                   |                  |    144    |   144   |  100.00 %   |                                                     
|   V3    |           asymmetric_read_path            | flash_ctrl_rd_ooo                        |      56.820s      |    250.333us     |     1     |    1    |  100.00 %   |                                                     
|   V3    |                                           | **TOTAL**                                |                   |                  |     1     |    1    |  100.00 %   |                                                     
|         |                                           | **TOTAL**                                |                   |                  |   1277    |  1278   |   99.92 %   |

## Failure Buckets                                      

* `UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: *` has 1 failures:                                         
    * Test flash_ctrl_rw_evict has 1 failures.                                                                   
        * 37.flash_ctrl_rw_evict.20990743793623703616760759244221730862183233247322056416938561136453286696213\                                                                                                                   
          Line 72, in log /home/dev/src/scratch/flash-ctrl-mask-fifo-fix/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest/run.log                                                                                                 

                UVM_ERROR @ 44755.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0                         
                UVM_INFO @ 44755.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]                                                                                                                                          
                --- UVM Report catcher Summary ---

INFO: [FlowCfg] [scratch_path]: [flash_ctrl] [/home/dev/src/scratch/flash-ctrl-mask-fifo-fix/flash_ctrl-sim-vcs]                                                                                                                  
ERROR: [dvsim] Errors were encountered in this run.                                                              

          [   legend    ]: [Q: queued, D: dispatched, P: passed, F: failed, K: killed, T: total]                 
00:00:49  [    build    ]: [Q: 0000, D: 0000, P: 0001, F: 0000, K: 0000, T: 0001] 100%                           
03:43:12  [     run     ]: [Q: 0000, D: 0000, P: 1277, F: 0001, K: 0000, T: 1278] 100%

@vogelpi vogelpi merged commit b745291 into lowRISC:master Apr 16, 2024
31 checks passed
@vogelpi vogelpi deleted the flash-ctrl-mask-fifo-fix branch April 18, 2024 21:50
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[rtl,flash_ctrl] Fix scrambler interface
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