[entropy_src] Fix handling of backpressure in the hardware pipeline

hw/ip/entropy_src/data/entropy_src.hjson

@@ -100,6 +100,13 @@
       local:   "false",
       expose:  "true"
     },
+    { name:    "DistrFifoDepth",
+      type:    "int unsigned",
+      default: "2",
+      desc:    "Number of 32-bit entries in the distr FIFO",
+      local:   "false",
+      expose:  "true"
+    },
     { name:    "Stub",
       type:    "bit",
       default: "0",
@@ -1615,6 +1622,14 @@
                 '''
         }
         { bits: "1",
+          name: "SFIFO_DISTR_ERR",
+          desc: '''
+                This bit will be set to one when an error has been detected for the distribution FIFO.
+                The type of error is reflected in the type status bits (bits 28 through 30 of this register).
+                This bit will stay set until the next reset.
+                '''
+        }
+        { bits: "2",
           name: "SFIFO_OBSERVE_ERR",
           desc: '''
                 This bit will be set to one when an error has been detected for the
@@ -1623,7 +1638,7 @@
                 This bit will stay set until the next reset.
                 '''
         }
-        { bits: "2",
+        { bits: "3",
           name: "SFIFO_ESFINAL_ERR",
           desc: '''
                 This bit will be set to one when an error has been detected for the
@@ -1679,27 +1694,21 @@
         { bits: "28",
           name: "FIFO_WRITE_ERR",
           desc: '''
-                This bit will be set to one when any of the source bits (bits 0 through 1 of this
-                this register) are asserted as a result of an error pulse generated from
-                any full FIFO that has been recieved a write pulse.
+                This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any full FIFO that has been received a write pulse.
                 This bit will stay set until the next reset.
                 '''
         }
         { bits: "29",
           name: "FIFO_READ_ERR",
           desc: '''
-                This bit will be set to one when any of the source bits (bits 0 through 1 of this
-                this register) are asserted as a result of an error pulse generated from
-                any empty FIFO that has recieved a read pulse.
+                This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any empty FIFO that has received a read pulse.
                 This bit will stay set until the next reset.
                 '''
         }
         { bits: "30",
           name: "FIFO_STATE_ERR",
           desc: '''
-                This bit will be set to one when any of the source bits (bits 0 through 1 of this
-                this register) are asserted as a result of an error pulse generated from
-                any FIFO where both the empty and full status bits are set.
+                This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any FIFO where either both the empty and full status bits are set or in case of error conditions inside the hardened counters.
                 This bit will stay set until the next reset.
                 '''
         }

hw/ip/entropy_src/doc/registers.md

@@ -1468,12 +1468,12 @@ Writing a zero resets this status bit.
 Hardware detection of error conditions status register
 - Offset: `0xd8`
 - Reset default: `0x0`
-- Reset mask: `0x71f00007`
+- Reset mask: `0x71f0000f`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "SFIFO_ESRNG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_OBSERVE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_ESFINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 17}, {"name": "ES_ACK_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ES_MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ES_CNTR_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHA3_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHA3_RST_STORAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 3}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+{"reg": [{"name": "SFIFO_ESRNG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_DISTR_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_OBSERVE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_ESFINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 16}, {"name": "ES_ACK_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ES_MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ES_CNTR_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHA3_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHA3_RST_STORAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 3}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
 ```
 
 |  Bits  |  Type  |  Reset  | Name                                                    |
@@ -1488,27 +1488,22 @@ Hardware detection of error conditions status register
 |   22   |   ro   |   0x0   | [ES_CNTR_ERR](#err_code--es_cntr_err)                   |
 |   21   |   ro   |   0x0   | [ES_MAIN_SM_ERR](#err_code--es_main_sm_err)             |
 |   20   |   ro   |   0x0   | [ES_ACK_SM_ERR](#err_code--es_ack_sm_err)               |
-|  19:3  |        |         | Reserved                                                |
-|   2    |   ro   |   0x0   | [SFIFO_ESFINAL_ERR](#err_code--sfifo_esfinal_err)       |
-|   1    |   ro   |   0x0   | [SFIFO_OBSERVE_ERR](#err_code--sfifo_observe_err)       |
+|  19:4  |        |         | Reserved                                                |
+|   3    |   ro   |   0x0   | [SFIFO_ESFINAL_ERR](#err_code--sfifo_esfinal_err)       |
+|   2    |   ro   |   0x0   | [SFIFO_OBSERVE_ERR](#err_code--sfifo_observe_err)       |
+|   1    |   ro   |   0x0   | [SFIFO_DISTR_ERR](#err_code--sfifo_distr_err)           |
 |   0    |   ro   |   0x0   | [SFIFO_ESRNG_ERR](#err_code--sfifo_esrng_err)           |
 
 ### ERR_CODE . FIFO_STATE_ERR
-This bit will be set to one when any of the source bits (bits 0 through 1 of this
-this register) are asserted as a result of an error pulse generated from
-any FIFO where both the empty and full status bits are set.
+This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any FIFO where either both the empty and full status bits are set or in case of error conditions inside the hardened counters.
 This bit will stay set until the next reset.
 
 ### ERR_CODE . FIFO_READ_ERR
-This bit will be set to one when any of the source bits (bits 0 through 1 of this
-this register) are asserted as a result of an error pulse generated from
-any empty FIFO that has recieved a read pulse.
+This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any empty FIFO that has received a read pulse.
 This bit will stay set until the next reset.
 
 ### ERR_CODE . FIFO_WRITE_ERR
-This bit will be set to one when any of the source bits (bits 0 through 1 of this
-this register) are asserted as a result of an error pulse generated from
-any full FIFO that has been recieved a write pulse.
+This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any full FIFO that has been received a write pulse.
 This bit will stay set until the next reset.
 
 ### ERR_CODE . SHA3_RST_STORAGE_ERR
@@ -1552,6 +1547,11 @@ observe FIFO. The type of error is reflected in the type status
 bits (bits 28 through 30 of this register).
 This bit will stay set until the next reset.
 
+### ERR_CODE . SFIFO_DISTR_ERR
+This bit will be set to one when an error has been detected for the distribution FIFO.
+The type of error is reflected in the type status bits (bits 28 through 30 of this register).
+This bit will stay set until the next reset.
+
 ### ERR_CODE . SFIFO_ESRNG_ERR
 This bit will be set to one when an error has been detected for the
 esrng FIFO. The type of error is reflected in the type status

hw/ip/entropy_src/dv/env/entropy_src_env.sv

@@ -58,10 +58,13 @@ class entropy_src_env extends cip_base_env #(
     cfg.m_aes_halt_agent_cfg.agent_type          = push_pull_agent_pkg::PullAgent;
     cfg.m_aes_halt_agent_cfg.if_mode             = dv_utils_pkg::Device;
     cfg.m_aes_halt_agent_cfg.pull_handshake_type = push_pull_agent_pkg::FourPhase;
-    // When CSRNG has just started operating its AES, it may take up to 48 cycles to acknowledge the
-    // request.
+    // When CSRNG has just started operating its AES, it may take up to 48 cycles to acknowledge
+    // the request. When running ast/rng at the maximum rate (this is an unrealistic scenario
+    // primarily used for reaching coverage metrics) we reduce the max acknowledge delay to
+    // reduce backpressure and avoid entropy bits from being dropped from the pipeline as our
+    // scoreboard cannot handle this.
     cfg.m_aes_halt_agent_cfg.zero_delays = 0;
-    cfg.m_aes_halt_agent_cfg.device_delay_max = 48;
+    cfg.m_aes_halt_agent_cfg.device_delay_max = (cfg.rng_max_delay == 1) ? 8 : 48;
     // CSRNG drops its ack in the cycle after entropy_src has dropped its req.
     cfg.m_aes_halt_agent_cfg.ack_lo_delay_max = 1;
 

hw/ip/entropy_src/dv/env/entropy_src_env_cfg.sv

@@ -182,14 +182,14 @@ class entropy_src_env_cfg extends cip_base_env_cfg #(.RAL_T(entropy_src_reg_bloc
   constraint which_err_code_c {
     which_err_code dist {
       sfifo_esrng_err   :/ 2,
-      sfifo_observe_err :/ 3,
+      sfifo_distr_err   :/ 2,
+      sfifo_observe_err :/ 2,
       sfifo_esfinal_err :/ 2,
       es_ack_sm_err     :/ 2,
       es_main_sm_err    :/ 2,
       es_cntr_err       :/ 60,
-      fifo_write_err    :/ 2,
-      fifo_read_err     :/ 3,
-      fifo_state_err    :/ 3};}
+      fifo_read_err     :/ 4,
+      fifo_state_err    :/ 4};}
 
   constraint which_cntr_replicate_c {which_cntr_replicate inside {[0:RNG_BUS_WIDTH-1]};}
   int        num_bins = 2**RNG_BUS_WIDTH;
@@ -207,17 +207,16 @@ class entropy_src_env_cfg extends cip_base_env_cfg #(.RAL_T(entropy_src_reg_bloc
   // Write errors no longer apply to the esfinal or esrng fifos
   // so exclude those combinations when targetting a specific fifo or error condition
   constraint which_fifo_err_c {
-    which_err_code inside {sfifo_esrng_err, sfifo_esfinal_err} ->
+    which_err_code inside {sfifo_esrng_err, sfifo_distr_err, sfifo_esfinal_err} ->
       which_fifo_err inside {read, state};
-    which_err_code == fifo_write_err -> which_fifo_err == write;
     which_err_code == fifo_read_err -> which_fifo_err == read;
     which_err_code == fifo_state_err -> which_fifo_err == state;
   }
 
   constraint which_fifo_c {
-    which_err_code == fifo_write_err -> which_fifo == sfifo_observe;
     which_err_code == sfifo_observe_err -> which_fifo == sfifo_observe;
     which_err_code == sfifo_esrng_err -> which_fifo == sfifo_esrng;
+    which_err_code == sfifo_distr_err -> which_fifo == sfifo_distr;
     which_err_code == sfifo_esfinal_err -> which_fifo == sfifo_esfinal;
   }
 

hw/ip/entropy_src/dv/env/entropy_src_env_pkg.sv

@@ -56,32 +56,33 @@ package entropy_src_env_pkg;
 
   typedef enum int {
     sfifo_esrng_err        = 0,
-    sfifo_observe_err      = 1,
-    sfifo_esfinal_err      = 2,
-    es_ack_sm_err          = 3,
-    es_main_sm_err         = 4,
-    es_cntr_err            = 5,
-    fifo_write_err         = 6,
+    sfifo_distr_err        = 1,
+    sfifo_observe_err      = 2,
+    sfifo_esfinal_err      = 3,
+    es_ack_sm_err          = 4,
+    es_main_sm_err         = 5,
+    es_cntr_err            = 6,
     fifo_read_err          = 7,
     fifo_state_err         = 8,
     sfifo_esrng_err_test   = 9,
-    sfifo_observe_err_test = 10,
-    sfifo_esfinal_err_test = 11,
-    es_ack_sm_err_test     = 12,
-    es_main_sm_err_test    = 13,
-    es_cntr_err_test       = 14,
-    fifo_write_err_test    = 15,
+    sfifo_distr_err_test   = 10,
+    sfifo_observe_err_test = 11,
+    sfifo_esfinal_err_test = 12,
+    es_ack_sm_err_test     = 13,
+    es_main_sm_err_test    = 14,
+    es_cntr_err_test       = 15,
     fifo_read_err_test     = 16,
     fifo_state_err_test    = 17
   } err_code_e;
 
   typedef enum int {
     sfifo_observe_error = 0,
     sfifo_esrng_error   = 1,
-    sfifo_esfinal_error = 2,
-    es_ack_sm_error     = 3,
-    es_main_sm_error    = 4,
-    es_cntr_error       = 5
+    sfifo_distr_error   = 2,
+    sfifo_esfinal_error = 3,
+    es_ack_sm_error     = 4,
+    es_main_sm_error    = 5,
+    es_cntr_error       = 6
   } fatal_err_e;
 
   typedef enum int {
@@ -121,8 +122,9 @@ package entropy_src_env_pkg;
 
   typedef enum int {
     sfifo_esrng   = 0,
-    sfifo_observe = 1,
-    sfifo_esfinal = 2
+    sfifo_distr   = 1,
+    sfifo_observe = 2,
+    sfifo_esfinal = 3
   } which_fifo_e;
 
   typedef enum int {
@@ -132,8 +134,9 @@ package entropy_src_env_pkg;
 
   typedef enum bit [4:0] {
     sfifo_esrng_err_code   = 0,
-    sfifo_observe_err_code = 1,
-    sfifo_esfinal_err_code = 2,
+    sfifo_distr_err_code   = 1,
+    sfifo_observe_err_code = 2,
+    sfifo_esfinal_err_code = 3,
     es_ack_sm_err_code     = 20,
     es_main_sm_err_code    = 21,
     es_cntr_err_code       = 22,

hw/ip/entropy_src/dv/env/seq_lib/entropy_src_err_vseq.sv

@@ -66,7 +66,7 @@ class entropy_src_err_vseq extends entropy_src_base_vseq;
     cfg.entropy_src_assert_vif.assert_off_err();
 
     case (cfg.which_err_code) inside
-      sfifo_esrng_err, sfifo_observe_err, sfifo_esfinal_err: begin
+      sfifo_esrng_err, sfifo_distr_err, sfifo_observe_err, sfifo_esfinal_err: begin
         path_name = cfg.which_fifo_err.name();
 
         path1 = cfg.entropy_src_path_vif.fifo_err_path(fifo_base_path,
@@ -126,7 +126,7 @@ class entropy_src_err_vseq extends entropy_src_base_vseq;
         `DV_CHECK(uvm_hdl_read(sm_state_path, sm_state))
         `DV_CHECK_EQ(sm_state, entropy_src_ack_sm_pkg::Error)
       end
-      fifo_write_err, fifo_read_err, fifo_state_err: begin
+      fifo_read_err, fifo_state_err: begin
         fifo_name = cfg.which_fifo.name();
         path_key = fld_name.substr(first_index+1, last_index-1);
 
@@ -141,16 +141,12 @@ class entropy_src_err_vseq extends entropy_src_base_vseq;
           fifo_forced_paths[i] = cfg.entropy_src_path_vif.fifo_err_path("sfifo_esrng",
                                                                         path_exts[i]);
         end
-        if (cfg.which_err_code == fifo_write_err && cfg.which_fifo == sfifo_esrng) begin
-          force_fifo_err_exception(fifo_forced_paths, fifo_forced_values, fld, 1'b1);
-        end else begin
-          force_fifo_err(path1, path2, value1, value2, fld, 1'b1);
-        end
+        force_fifo_err(path1, path2, value1, value2, fld, 1'b1);
         cov_vif.cg_fifo_err_sample(cfg.which_fifo_err, cfg.which_fifo);
       end
-      sfifo_esrng_err_test ,sfifo_observe_err_test, sfifo_esfinal_err_test, es_ack_sm_err_test,
-      es_main_sm_err_test, es_cntr_err_test, fifo_write_err_test, fifo_read_err_test,
-      fifo_state_err_test: begin
+      sfifo_esrng_err_test, sfifo_distr_err_test, sfifo_observe_err_test, sfifo_esfinal_err_test,
+      es_ack_sm_err_test, es_main_sm_err_test, es_cntr_err_test,
+      fifo_read_err_test, fifo_state_err_test: begin
         // First turn off module_enable to write registers
         csr_wr(.ptr(ral.module_enable), .value(prim_mubi_pkg::MuBi4False));
         // Get the register field name

hw/ip/entropy_src/rtl/entropy_src.sv

@@ -14,7 +14,8 @@ module entropy_src
 #(
   parameter bit Stub = 1'b0,
   parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
-  parameter int EsFifoDepth = 4
+  parameter int EsFifoDepth = 4,
+  parameter int DistrFifoDepth = 2
 ) (
   input logic clk_i,
   input logic rst_ni,
@@ -130,7 +131,8 @@ module entropy_src
   );
 
   entropy_src_core #(
-    .EsFifoDepth(EsFifoDepth)
+    .EsFifoDepth(EsFifoDepth),
+    .DistrFifoDepth(DistrFifoDepth)
   ) u_entropy_src_core (
     .clk_i,
     .rst_ni(core_rst_n),
@@ -403,6 +405,35 @@ module entropy_src
     u_entropy_src_core.u_entropy_src_cntr_reg_extht_lo_alert_fails.u_prim_count_cntr_reg,
     alert_tx_o[1])
 
+  `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(EsrngFifoWptrCheck_A,
+    u_entropy_src_core.u_prim_fifo_sync_esrng.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr,
+    alert_tx_o[1])
+  `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(EsrngFifoRptrCheck_A,
+    u_entropy_src_core.u_prim_fifo_sync_esrng.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr,
+    alert_tx_o[1])
+
+  `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(DistrFifoWptrCheck_A,
+    u_entropy_src_core.u_prim_fifo_sync_distr.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr,
+    alert_tx_o[1])
+  `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(DistrFifoRptrCheck_A,
+    u_entropy_src_core.u_prim_fifo_sync_distr.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr,
+    alert_tx_o[1])
+
+  `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(ObserveFifoWptrCheck_A,
+    u_entropy_src_core.u_prim_fifo_sync_observe.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr,
+    alert_tx_o[1])
+  `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(ObserveFifoRptrCheck_A,
+    u_entropy_src_core.u_prim_fifo_sync_observe.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr,
+    alert_tx_o[1])
+
+  `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(EsfinalFifoWptrCheck_A,
+    u_entropy_src_core.u_prim_fifo_sync_esfinal.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr,
+    alert_tx_o[1])
+  `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(EsfinalFifoRptrCheck_A,
+    u_entropy_src_core.u_prim_fifo_sync_esfinal.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr,
+    alert_tx_o[1])
+
   // Alert assertions for reg_we onehot check
   `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[1])
+
 endmodule